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V124S Driver Design Review

V124S Driver Design Review. Johnny Tang (BNL) SNS Global Controls. Outline. V124S Driver Design Requirements V124S Board VME Memory Map and Register Bit Assignments V124S Driver Design Block Diagram V124S Driver - bsTrigDrv Overview Default Mode Device Names IOCTL Functions

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V124S Driver Design Review

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  1. V124S Driver Design Review Johnny Tang (BNL) SNS Global Controls

  2. Outline • V124S Driver Design Requirements • V124S Board VME Memory Map and Register Bit Assignments • V124S Driver Design Block Diagram • V124S Driver - bsTrigDrv • Overview • Default Mode • Device Names • IOCTL Functions • Interrupt Handling • EPICS Interface • New Customized Record vs. Record Template • EPICS Device Support • V124S Documentations • Summary – Current Status

  3. V124S Driver Design Requirements • Compatible with SNS ADE • Provide Board Configuration & Status Access Routines • Support V124S Board Functionalities • Compliant with Wind River Coding Conventions • VxWorks naming conventions (routines, variables, constants, macros, types, structure and error status codes) • Unique status codes assigned for each error • Subroutines must be preceded by a comment block containing the purpose of the subroutine • Parameterize base address, interrupt number & vector

  4. V124S VME Memory Map and Bit Assignments

  5. Event Mask RAM Bit Definitions If the Sub-Revolution Counter Enable Selector is selected to be an Event, the Revolution Counter Enable Selector will be ignored.

  6. Board Configuration Registers The following registers and bit assignments are global and affect all channels BaseAddr+0040: rd/wr Command Register bit 0 – Module Enable: set when configuration is complete bit 1 – Ref/*Auto: Ref Oscillator/LinkClk BaseAddr+0041: rd/wr Interrupt Level bit 0-2 – Interrupt Level BaseAddr+0044: rd/wr SYNC Event Code for Revolution Frequency ReSync BaseAddr+0046: rd/wr SYNC Event Code for Timestamp Reset BaseAddr+004E: rd/wr RF Clock/Link Clock Delay BaseAddr+004F: rd/wr Text Event Code BaseAddr+0050: rd/wr PrePulse Event Code BaseAddr+0051: rd/wr T0 Event Code

  7. Channel Configuration Registers 32 bytes of channel configuration data are allocated per channel as follows (offset from BaseAddr): 0440-045f Channel 1 04c0-04df Channel 2 0540-055f Channel 3 05c0-05df Channel 4 0640-065f Channel 5 06c0-06df Channel 6 0740-075f Channel 7 07c0-07df Channel 8

  8. Channel Delay control register and bit assignments Each channel has a Delay Control Register: BaseAddr+ChannelX_Offset: rd/wr Delay Control Register bit 0 - Reload Counters on Trigger Counter Terminal Count bit 1 – RESERVED bit 2 – RESERVED bit 3 - RESERVED bit 4 – VMEbus Trigger Command bit 5 – VMEbus Reset Command - Clears all counter and command Values 0 = not Reset 1 = Reset bit 6 - STOP - halts counting of all counters 0 = Count 1 = Stop bit7 - Output Polarity 0 = Non-inverted 1 = Inverted

  9. Channel Counter Control register and bit assignments Each channel has a Counter Control Register: BaseAddr+ChannelX_Offset+1: rd/wr Counter Control Register bit 1,0 – Revolution Delay Enable Selector 00 – VMEbus 01 – Event 10 – External 11 – Previous Channel (not Channel 1) bit 3,2 – Sub-Revolution Delay Enable Selector 00 – VMEbus 01 – Event 10 – Revolution Delay Enable/Revolution Delay Counter Terminal Count 11 – Revolution Delay Counter Terminal Count bit 5,4 – Halt Delay Clock Select 00 – Fine Delay Clock 01 – No Halt 10 – Not Used 11 – Next Channel (not Channel 8) bit 6 – Pulse Width Enable Select 0 – Sub-Revolution Delay Counter Terminal Count bit 7 – Fine Delay Clock Select 0 – Fixed Pulse Width (118ns) 1 – Variable Pulse Width

  10. Channel Counter Status Flag register and bit assignments Each Channel has a Counter Status Flag Register BaseAddr+ChannelX_Offset+3: rd Counter Status Flags A 1 in any of the following bit locations indicates that the condition is true. bit 0 – Waiting for Revolution Delay Enable bit 1 – Waiting for Revolution Delay Terminal Count bit 2 - Waiting for Sub-Revolution Delay Enable bit 3 – Waiting for Sub-Revolution Delay Terminal Count bit 4 – Waiting for Trigger Terminal Count

  11. Channel Delay Hold Registers 16 bit rev counter register from 1 (945ns) to 65536 (61.97ms) BaseAddr+ChannelX_Offset+8: rd/wr msbyte Revolution Delay Hold Register BaseAddr+ChannelX_Offset+9: rd/wr lsbyte Revolution Delay Hold Register BaseAddr+ChannelX_Offset+b: rd lsbyte Revolution Delay Counter Value 8 bit sub-rev counter from 1 to 255 of 1/32 * Frev BaseAddr+ChannelX_Offset+d: rd/wr lsbyte Sub-Revolution Delay Hold Register BaseAddr+ChannelX+f: rd lsbyte Sub-Revolution Delay Counter Value

  12. Channel Trigger Hold Register 32 bit trigger pulse counter (1 to 4.29E9) BaseAddr+ChannelX_Offset+10h: rd/wr msbyte Trigger Hold Register BaseAddr+ChannelX_Offset+11h: rd/wr Trigger Hold Register BaseAddr+ChannelX_Offset+12h: rd/wr Trigger Hold Register BaseAddr+ChannelX_Offset+13h: rd/wr lsbyte Trigger Hold Register

  13. Channel Pulse Width Hold Register 16 bit pulse width counter from 1 (29.5ns) to 65536 (1.94ms) of 1/32 * Frev BaseAddr+ChannelX_Offset+14h: rd/wr msbyte Pulse Width Hold Register BaseAddr+ChannelX_Offset+15h: rd/wr lsbyte Pulse Width Hold Register

  14. Channel Fine Delay Hold Register BaseAddr+ChannelX_Offset+16h: rd/wr Fine Delay Hold Register 8 bit fine delay from 0 (12ns latency) to 255 (139.5ns) of 500 ps

  15. Channel Timestamp Registers BaseAddr+ChannelX+Offset+19h: rd/wr Beam Synchronous Event Timestamp Code BaseAddr+ChannelX+Offset+1Ah: rd/wr Timestamp Configuration Register bit 0 – Timestamp on a Beam Synchronous Event bit 1 – Timestamp on First Output Pulse (of a series). bit 2 – Timestamp on Halt Trigger bit 3 – Timestamp Clock Source 0 – 945ns clock derived from the carrier frequency 1 – a Beam Synchronous Event BaseAddr+ChannelX+Offset+1Bh: rd/wr Beam Synchronous Event Code for Timestamp Clock Source BaseAddr+ ChannelX+Offset+ 1ch: rd msbyte Timestamp Value BaseAddr+ ChannelX+Offset+ 1dh: rd Timestamp Value BaseAddr+ ChannelX+Offset+ 1eh: rd Timestamp Value BaseAddr+ ChannelX+Offset+ 1fh: rd lsbyte Timestamp Value

  16. Interrupt Enable Registers BaseAddr+2: rd/wr Interrupt Enable bit 0 - Channel 1 Trigger Terminal Count bit 1 - Channel 2 Trigger Terminal Count bit 2 - Channel 3 Trigger Terminal Count bit 3 - Channel 4 Trigger Terminal Count bit 4 - Channel 5 Trigger Terminal Count bit 5 - Channel 6 Trigger Terminal Count bit 6 - Channel 7 Trigger Terminal Count bit 7 - Channel 8 Trigger Terminal Count BaseAddr+3: rd/wr Interrupt Enable The interrupt is enabled when the corresponding bit is high. bit 0 - bit 1 - bit 2 - bit 3 - Beam Synchronous Link Carrier error bit 4 - Beam Synchronous Link Frame error bit 5 - Beam Synchronous Link Parity error bit 6 - Timestamp SYNC Event bit 7 - Timestamp source

  17. Interrupt Status Register BaseAddr+5: rd Interrupt Status Register This register indicates the cause of the interrupt. When this register is read, the interrupt request on the VMEbus WILL be cleared. The interrupt status bit in this register will remain in a logic 1 state until the error condition is cleared. If the interrupt is caused by an Event Link Error or a Beam Sync Link Error, Interrupt source register (BaseAddr+9) Must be read to determine the actual cause of the interrupt. If a Channel Halt interrupt occurs, Interrupt source register (BaseAddr+b) must be read to determine which Channel Halt occurred. If a Timestamp Trigger interrupt occurs, Interrupt Source Register (BaseAddr+d) must be read to determine which channel timestamp occurred. bit 0 - reserved bit 1 - reserved bit 2 - reserved bit 3 – Beam Synchronous Link Error bit 4 – Channel Trigger Terminal Count bit 5 - reserved bit 6 - Timestamp SYNC Event bit 7- Timestamp source

  18. Interrupt Vector Register BaseAddr+7: rd/wr interrupt vector bit 0-7 – VME Interrupt Vector

  19. Link Status and Link Interrupt Source Registers BaseAddr+8: rd Links Status The bits in this register are identical to the interrupt status register, addr BaseAddr+9. Reading this register will NOT cause the interrupt to be cleared. The front end computer may poll this register after an interrupt occurs to determine if the error condition still exists.  bit 0 - bit 1 - bit 2 - bit 3 - Beam Synchronous Link Carrier error bit 4 - Beam Synchronous Link Frame error bit 5 - Beam Synchronous Link Parity error bit 6 - Timestamp SYNC Event bit 7 – BaseAddr+9: rd Interrupt Source: Links This register indicates the source of an interrupt. This register must be read by the interrupt handler if an Event Link or a Beam Sync Link Interrupt occurred. Reading this register will clear the Interrupt Source.  bit 0 - bit 1 - bit 2 - bit 3 - Beam Sync Link Carrier error bit 4 - Beam Sync Link Frame error bit 5 - Beam Sync Link Parity error bit 6 - Timestamp SYNC Event bit 7 -

  20. Trigger Terminial Count Status and Interrupt Source Registers BaseAddr+a: rd Trigger Terminal Count Status The bits in this register are identical to the interrupt status register, addr BaseAddr+b. Reading this register will NOT cause the interrupt to be cleared. The front end computer may poll this register after an interrupt occurs to determine if the channel is still in the Terminal Count state.  bit 0 - Channel 1 bit 1 - Channel 2 bit 2 - Channel 3 bit 3 - Channel 4 bit 4 - Channel 5 bit 5 - Channel 6 bit 6 - Channel 7 bit 7 - Channel 8 BaseAddr+b: rd Interrupt Source: Trigger Terminal Count This register indicates the source of an interrupt. This register must be read by the interrupt handler if a Trigger Terminal Count Interrupt occurred. Reading this register will clear the Interrupt Source.  bit 0 - Channel 1 bit 1 - Channel 2 bit 2 - Channel 3 bit 3 - Channel 4 bit 4 - Channel 5 bit 5 - Channel 6 bit 6 - Channel 7 bit 7 - Channel 8

  21. Timestamp Status and Interrupt Source Registers BaseAddr+d: rd Interrupt Source: Timestamp This register indicates the source of an interrupt. This register must be read by the interrupt handler if a Timestamp Interrupt occurred. Reading this register will clear the Interrupt Source. bit 0 - Channel 1 bit 1 - Channel 2 bit 2 - Channel 3 bit 3 - Channel 4 bit 4 - Channel 5 bit 5 - Channel 6 bit 6 - Channel 7 bit 7 - Channel 8 BaseAddr+c: rd Timestamp Status The bits in this register are identical to the interrupt status register, addr BaseAddr+d. Reading this register will NOT cause the interrupt to be cleared. The front end computer may poll this register after an interrupt occurs to determine if the channel timestamp has been read. bit 0 - Channel 1 bit 1 - Channel 2 bit 2 - Channel 3 bit 3 - Channel 4 bit 4 - Channel 5 bit 5 - Channel 6 bit 6 - Channel 7 bit 7 - Channel 8

  22. V124S Driver Design Block Diagram Application V124S IOC Startup Script EPICS Support Layer close() ioctl() open() ioLib iosDrvInstall() iosLib iosDevAddl() bsTrigOpen() bsTrigDrv() bsTrigDevCreate() bsTrigIoctl() bsTrigClose() bsTrigDrv

  23. V124S Driver – bsTrigDrv.c - Initialization • Initialization This driver provides an interface to the V124 8-channel, beam-synchronous trigger module. The driver allows configuring each of the 8 channels individually. Most of the routines in this driver are accessible only through the I/O system. bsTrigDrv(), however, must be called directly to install the driver and bsTrigDevCreate() to initialize and install each device. After installing the driver and creating the devices the following functions are available; open(), close(), ioctl(). These are available through the VxWorks I/O system. bsTrigDrv(void) #Install driver bsTrigDevCreate - Create each beam-sync trigger device int bsTrigDevCreate(deviceName, baseAddress, intNumber, intLevel, syncEventCode, positionDelay, offTime); char *deviceName  # Name of V124s trigger module device (e.g. /dev/bsA).  void *baseAddress # V124S base address.  unsigned char intNumber  # Interrupt number.  unsigned char intLevel  # VMEbus interrupt level. unsigned char syncEventCode  # Code of sync event on BS event link. unsigned char TSResetEventCode  # Code for Timestamp Reset. unsigned char clockDelay # RF Clock Delay   

  24. V124S Driver – bsTrigDrv.c – Device Names • Device Names For this device driver, a VxWorks logical device will be defined as a single V124S trigger module. Each trigger module within each IOC system will have a unique device name. The driver supports arbitrary names. However, it is recommended that, for ease of use, device names reflect the function or position of the device in the system. Extended naming will be used when using open() to access one of the eight trigger output channels (numbered channels 0-7) on a V124S module. E.g. if the name of the V124S device is "/dev/bsA", the name of channel 0 is "/dev/bsA/0", and the name of channel 7 is "/dev/bsA/7".

  25. V124S Driver – bsTrigDrv.c – IOCTL Function List • Supported IOCTL Functions BS_TRIG_CLOCK_MODEBS_TRIG_SET_SYNC_EVENTBS_TRIG_GET_SYNC_EVENTBS_TRIG_SET_REVOLUTION_COUNTERBS_TRIG_GET_REVOLUTION_COUNTERBS_TRIG_READ_REVOLUTION_COUNTER_LSBBS_TRIG_SET_SUBREV_COUNTERBS_TRIG_GET_SUBREV_COUNTERBS_TRIG_READ_SUBREV_COUNTER_LSBBS_TRIG_SET_TRIGGER_COUNTERBS_TRIG_GET_TRIGGER_COUNTERBS_TRIG_SET_PULSE_WIDTHBS_TRIG_GET_PULSE_WIDTHBS_TRIG_SET_FINE_DELAYBS_TRIG_GET_FINE_DELAYBS_TRIG_SET_TIMESTAMP_TRIGGER_EVENTBS_TRIG_GET_TIMESTAMP_TRIGGER_EVENTBS_TRIG_GET_TIMESTAMP_VALUEBS_TRIG_SET_EVENT_MASKBS_TRIG_CLEAR_EVENT_MASKBS_TRIG_GET_EVLINK_CARRIER_ERRORBS_TRIG_GET_EVLINK_FRAME_ERRORBS_TRIG_GET_EVLINK_PARITY_ERRORBS_TRIG_GET_CHANNEL_STATUSBS_TRIG_SET_TIMESTAMP_EVENT_CODEBS_TRIG_GET_TIMESTAMP_EVENT_CODEBS_TRIG_SW_TRIGGERBS_TRIG_SUBREV_COUNTER_ENABLEBS_TRIG_REVOLUTION_COUNTER_ENABLEBS_TRIG_HALT_TRIGGER_CLOCKBS_TRIG_RELOAD_ALL_COUNTERSBS_TRIG_HALT_COUNTERSBS_TRIG_OUTPUT_POLARITYBS_TRIG_RESET_COUNTERSBS_TRIG_RELOAD_COUNTERSBS_TRIG_RELOAD_REV_COUNTERBS_TRIG_LINK_STATUS_OKBS_TRIG_WAIT_TIMEBS_TRIG_WAIT

  26. BS_TRIG_CLOCK_MODE Description: Set or query the clock mode. The system clock is usually based  on the beam-sync link carrier, but can be set to an internal xtal oscillator  for test purposes. The setting is usually controlled when the device is  first created. This function is provided to support debugging efforts. Arg Usage: BS_TRIG_CLOCK_MODE, BS_TRIG_CLOCK_TEST_MODE, BS_TRIG_CLOCK_MODE_QUERY  Return Value: OK, or current setting if arg is BS_TRIG_CLOCK_MODE_QUERY V124S Driver – bsTrigDrv.c – IOCTL Functions

  27. BS_TRIG_SET_SYNC_EVENT Description: Set the timestamp resynchronizing event. The setting is usually controlled when  the device is first created. This function is provided to support debugging efforts. Arg Usage: Event code for beam-sync event to be used as sync event  (reset timestamp counters) Return Value: OK BS_TRIG_GET_SYNC_EVENT Description: Return the sync event.  Arg Usage: N/A Return Value: Sync event code V124S Driver – bsTrigDrv.c – IOCTL Functions

  28. BS_TRIG_SET_REVOLUTION_COUNTER Description: Provide a value for the "revolution counter". This 16 bit counter can be set from 1 (945ns) to 65536 (61.97ms). Arg Usage: 16-bit revolution counter value Return Value: OK V124S Driver – bsTrigDrv.c – IOCTL Functions

  29. BS_TRIG_GET_REVOLUTION_COUNTER Description: Return the 16-bit revolution counter. Arg Usage: N/A Return Value: Revolution counter value BS_TRIG_READ_REVOLUTION_COUNTER_LSB Description: For diagnostic purposes, it is possible to read the 8 least  significant bits of the actual revolution counter, as it is  counting down. This is especially useful is a lab environment  where the revolution fiducial may occur at 1 Hz, or even slower.  This feature probably has no operational use. Arg Usage: N/A Return Value: Least significant byte of the revolution counter V124S Driver – bsTrigDrv.c – IOCTL Functions

  30. BS_TRIG_SET_SUBREV_COUNTER Description: Provide a sub-revolution delay count value.It can be set to from 1 to 255 of 1/32*Frev. Arg Usage: 8 bit delay (1/32 * Frev) Return Value: OK BS_TRIG_GET_SUBREV_COUNTER Description: Return the sub-rev delay value Arg Usage: N/A Return Value: 8 bit sub-rev delay BS_TRIG_READ_SUBREV_COUNTER_LSB Description: Just as for the revolution counter, there is a provision to  monitor the least significant 8 bits of the subrev counter.  Arg Usage: N/A Return Value: least significant 8 bits of sub-revolution delay V124S Driver – bsTrigDrv.c – IOCTL Functions

  31. BS_TRIG_SET_TRIGGER_COUNTER Description: The V124S provides a 32-bit trigger counter. By default, this counter  counts leading edges of the output pulses generated for this channel.  When the counter reaches 0, a "halt trigger" is issued for the channel.  The halt trigger is normally used to terminate a timing sequence. The  halt trigger can also be used to generate a timestamp for a timing  sequence,  and it can be used to automatically restart a timing sequence. In  addition, the driver provides a mechanism for synchronizing software  with the occurrence of a halt trigger. Arg Usage: 32-bit halt trigger count Return Value: OK BS_TRIG_GET_TRIGGER_COUNTER Description: Return the 32-bit halt trigger value. Arg Usage: N/A Return Value: 32-bit halt trigger value V124S Driver – bsTrigDrv.c – IOCTL Functions

  32. BS_TRIG_SET_PULSE_WIDTH Description: 16 bit pulse width counter can be set to from 1(29.5ns) to 65536 (1.94ms) of 1/32 * Frev. It also can be set to a fix width of 118ns. Arg Usage: 16-bit pulse width, or BS_TRIG_PULSE_WIDTH_118NS fixed width Return Value: OK, or ERROR when setting BS_TRIG_PULSE_WIDTH_118NS while not in bucket pattern mode BS_TRIG_GET_PULSE_WIDTH Description: Return the 16-bit pulse width counter value. Arg Usage: N/A Return Value: Pulse width counter, or BS_TRIG_PULSE_WIDTH_118NS fixed pulse width. V124S Driver – bsTrigDrv.c – IOCTL Functions

  33. BS_TRIG_SET_FINE_DELAY Description: Provide an 8-bit fine delay. It can be set to from 0 (12ns latency) to 255 (139.5ns). Resolution is 500ps. Arg Usage: N/A Return Value: OK BS_TRIG_GET_FINE_DELAY Description: Return the fine counter value. Arg Usage: N/A Return Value: 8-bit fine delay value V124S Driver – bsTrigDrv.c – IOCTL Functions

  34. BS_TRIG_SET_TIMESTAMP_TRIGGER_EVENT Description: Configure the event which causes the timestamp to be generated,  and the timestamp interrupt to occur. This event can be an event  on the beam-sync event link, or it can be the occurrence of the first  output pulse of a sequence of pulses (delineated by halt events),  or it can be the occurrence of a halt event. Arg Usage: BS_TRIG_TIMESTAMP_TRIGGER_EVENT_FIRST_PULSE,  BS_TRIG_TIMESTAMP_TRIGGER_EVENT_LAST_PULSE,  or a beam-sync event code Return Value: OK BS_TRIG_GET_TIMESTAMP_TRIGGER_EVENT Description: Return value of timestamp trigger event Arg Usage: N/A Return Value: BS_TRIG_TIMESTAMP_TRIGGER_EVENT_FIRST_PULSE,  BS_TRIG_TIMESTAMP_TRIGGER_EVENT_LAST_PULSE,  or a beam-sync event code BS_TRIG_GET_TIMESTAMP_VALUE Description: Return last recorded timestamp value. The timestamp is recorded  when the timestamp trigger event occurs. The timestamp counter is  cleared when the sync event occurs. The timestamp counter can be  advanced by a 1 Frev (945ns) clock derived from the event-link  carrier frequency, or by the  occurrence of an event on the beam-sync event link. Arg Usage: N/A Return Value: 32-bit timestamp V124S Driver – bsTrigDrv.c – IOCTL Functions

  35. BS_TRIG_SET_EVENT_MASK Description: Add an event to the set of beam-sync events which trigger  ANY event triggerable component of this channel.  Typically, events trigger the revolution counter. Arg Usage: beam-sync event code number Return Value: OK BS_TRIG_CLEAR_EVENT_MASK Description: Remove an event from the set of events which  trigger this channel. Arg Usage: beam-sync event code number Return Value: OK V124S Driver – bsTrigDrv.c – IOCTL Functions

  36. BS_TRIG_GET_EVLINK_CARRIER_ERROR Description: Return count of state changes in beam-sync  event-link carrier error monitoring. Arg Usage: N/A Return Value: count of state changes BS_TRIG_GET_EVLINK_FRAME_ERROR Description: Return count of state changes in beam-sync  event-link frame error monitoring. Arg Usage: N/A Return Value: count of state changes BS_TRIG_GET_EVLINK_PARITY_ERROR Description: Return count of state changes in beam-sync  event-link parity error monitoring. Arg Usage: N/A Return Value: count of state changes V124S Driver – bsTrigDrv.c – IOCTL Functions

  37. BS_TRIG_GET_CHANNEL_STATUS Description: For diagnostic purposes, it is possible to monitor the  state of event processing within the V124S. This  feature probably has no operational use. Arg Usage: N/A Return Value: The logical OR of any of these values :  BS_TRIG_STATUS_WAITING_FOR_REVOLUTION_CNTR_ENABLE ,  BS_TRIG_STATUS_WAITING_FOR_CNTR_DONE,  BS_TRIG_STATUS_WAITING_FOR_SUBREV_CNTR_ENABLE,  BS_TRIG_STATUS_WAITING_FOR_SUBREV_CNTR_DONE,  BS_TRIG_STATUS_WAITING_FOR_TRIGGER_CNTR_DONE,  BS_TRIG_STATUS_RESET V124S Driver – bsTrigDrv.c – IOCTL Functions

  38. BS_TRIG_SET_TIMESTAMP_EVENT_CODE Description: Sets the event which advances the timestamp counter. The  event can be an event on the beam-sync event link, or it can  a Frev (945ns) clock derived from the carrier on the event link  Arg Usage: BS_TRIG_TIMESTAMP_EVENT_945NS, or beam-sync event code Return Value: OK BS_TRIG_GET_TIMESTAMP_EVENT_CODE Description: Return event which advances the timestamp counter. Arg Usage: N/A Return Value: BS_TRIG_TIMESTAMP_EVENT_10MHZ, or beam-sync event code V124S Driver – bsTrigDrv.c – IOCTL Functions

  39. BS_TRIG_SW_TRIGGER Description: Trigger revolution counter or sub-rev counter, if  either is so programmed. Arg Usage: N/A Return Value: OK V124S Driver – bsTrigDrv.c – IOCTL Functions

  40. BS_TRIG_SUBREV_COUNTER_ENABLE Description: Set or query the subrev counter enable mode. Normally, the subrev counter is  enabled by the revolution counter terminal count. However, for certain triggering modes,  it might be desirable to enable the subrev counter as soon as an event occurs, rather than  waiting for the next revolution fiducial. This function allows bypassing the revolution  counter for such triggering modes. This function also allows bypassing the revolution  counter when initiating a timing sequence via software. However, due to the uncertain  timing associated with software triggering, there is little advantage to bypassing the revolution  counter except for diagnostic purposes. Arg Usage: BS_TRIG_SUBREV_COUNTER_ENABLE_SW,  BS_TRIG_SUBREV_COUNTER_ENABLE_EVENT,  BS_TRIG_SUBREV_COUNTER_ENABLE_REV_COUNTER,  BS_TRIG_SUBREV_COUNTER_ENABLE_QUERY Return Value: OK, or current setting if arg is BS_TRIG_BUCKET_COUNTER_ENABLE_QUERY V124S Driver – bsTrigDrv.c – IOCTL Functions

  41. BS_TRIG_REVOLUTION_COUNTER_ENABLE Description: The revolution counter can be enabled by a beam-synchronous event, via an  external signal (there is one external signal for each pair of output channels),  via software, or via the leading edge of an output pulse generated by the  previous channel (except for the first channel). Arg Usage: BS_TRIG_REVOLUTION_COUNTER_ENABLE_SW,  BS_TRIG_REVOLUTION_COUNTER_ENABLE_EVENT,  BS_TRIG_REVOLUTION_COUNTER_ENABLE_EXTERNAL,  BS_TRIG_REVOLUTION_COUNTER_ENABLE_PREVIOUS,  BS_TRIG_REVOLUTION_COUNTER_ENABLE_QUERY Return Value: OK, or current setting if arg is BS_TRIG_REVOLUTION_COUNTER_ENABLE_QUERY V124S Driver – bsTrigDrv.c – IOCTL Functions

  42. BS_TRIG_HALT_TRIGGER_CLOCK Description: The halt trigger can be used to terminate a timing sequence after a  specified number of pulses have been generated. The trigger counter  can be incremented on the leading edge of an output pulse for this  channel, or by the sub-rev counter terminal count for the next channel  (except the last channel). Arg Usage: BS_TRIG_HALT_TRIGGER_ENABLE_PULSE,  BS_TRIG_HALT_TRIGGER_ENABLE_NOT,  BS_TRIG_HALT_TRIGGER_ENABLE_NEXT,  BS_TRIG_HALT_TRIGGER_ENABLE_QUERY Return Value: OK, or current setting if arg is BS_TRIG_HALT_TRIGGER_ENABLE_QUERY  V124S Driver – bsTrigDrv.c – IOCTL Functions

  43. BS_TRIG_RELOAD_ALL_COUNTERS Description: Restore all counters to their previous values. This function  is necessary for manually repeating a one-shot timing sequence. Arg Usage: N/A Return Value: OK BS_TRIG_HALT_COUNTERS Description: Set or query the counter halt state. Halting the counters  may be necessary during periods of channel reconfiguration.  E.g. If the revolution counter is armed by a regularly  occurring beam-sync event, it may be necessary to halt  counters while reloading counter values to avoid premature  initiation of the timing sequence. The same effect could  be accomplished in other ways, however, those other techniques  require more understanding of the configuration of the channel.  This function suspends channel operation without otherwise  affecting channel configuration. Arg Usage: BS_TRIG_TRIGGER_HALT,  BS_TRIG_TRIGGER_RESUME,  BS_TRIG_TRIGGER_HALT_QUERY Return Value: OK, or current setting if arg is BS_TRIG_TRIGGER_HALT_QUERY V124S Driver – bsTrigDrv.c – IOCTL Functions

  44. BS_TRIG_OUTPUT_POLARITY Description: Set or query the output pulse polarity  (active high or active low). Arg Usage: BS_TRIG_OUTPUT_POLARITY_POSITIVE,  BS_TRIG_OUTPUT_POLARITY_NEGATIVE,  BS_TRIG_OUTPUT_POLARITY_QUERY Return Value: OK, or current setting if arg is BS_TRIG_OUTPUT_POLARITY_QUERY BS_TRIG_RESET_COUNTERS Description: Sets all counter values to 0 Arg Usage: N/A Return Value: OK V124S Driver – bsTrigDrv.c – IOCTL Functions

  45. BS_TRIG_RELOAD_COUNTERS Description: The counters can be configured to reload when a halt condition  occurs. This allows continuous generation of a timing sequence.  Alternatively, the timing sequence can be terminated when a  halt condition occurs. In that case, the counters must be  manually reloaded after the halt condition occurs. Arg Usage: BS_TRIG_RELOAD_COUNTERS_ON_HALT,  BS_TRIG_RELOAD_COUNTERS_MANUALLY,  BS_TRIG_RELOAD_COUNTERS_QUERY Return Value: OK, or current setting if arg is BS_TRIG_RELOAD_COUNTERS_QUERY  BS_TRIG_RELOAD_REV_COUNTER Description: The revolution counter can be configured to reload when  the subrev delay is enabled.  Arg Usage: BS_TRIG_RELOAD_REV_COUNTER_ON_TRIGGER,  BS_TRIG_RELOAD_REV_COUNTER_MANUALLY,  BS_TRIG_RELOAD_REV_COUNTER_QUERY Return Value: OK, or current setting if arg is BS_TRIG_RELOAD_REV_COUNTER_QUERY  V124S Driver – bsTrigDrv.c – IOCTL Functions

  46. BS_TRIG_LINK_STATUS_OK Description: Return the current status of the eventlink indicated in arg. Arg Usage: BS_TRIG_EVLINK_OK,  Return Value: OK, or ERROR is eventlink malfunction is detected BS_TRIG_WAIT_TIME Description: Sets the number of system ticks to wait for condition to occur  before timing out. By default, there is no time limit, i.e.  The BS_TRIG_WAIT function will wait forever for the  indicated condition to occur. Arg Usage: Number of system ticks to wait for condition. Return Value: OK V124S Driver – bsTrigDrv.c – IOCTL Functions

  47. BS_TRIG_WAIT Description: Wait for indicated condition to occur. The time limit is  infinite by default, but can be shortened using BS_TRIG_WAIT_TIME.  The timestamp condition occurs when a new timestamp becomes  available for a channel. This can be configured to occur when the  first pulse of a sequence is generated, when a halt condition occurs, or  when a particular beam-sync event occurs. Waiting for this condition  could be useful for synchronizing software with beam-sync events.  The sync condition occurs every time the timestamp resynchronizing  event occurs. Waiting for this condition could be useful for synchronizing  software with resetting of timestamp counters, e.g. to record the  time-of-day when the resynchronizing event occurred.  The halt condition occurs at the termination of the timing sequence.  The channel may be configured so that a new timing sequence is  immediately initiated. Waiting for the halt condition can be useful  for software which needs to process day at the end of each timing sequence. Arg Usage: BS_TRIG_WAIT_TIMESTAMP,  BS_TRIG_WAIT_HALT,  BS_TRIG_WAIT_SYNC Return Value: OK if condition occurred, ERROR if timeout occurred V124S Driver – bsTrigDrv.c – IOCTL Functions

  48. V124S Driver – bsTrigDrv.c – Interrupt Handling The ISR stores timestamp values as they occur, and accumulates link failure statistics. The ISR also provides user notification of sync events and/or channel halt events when they occur. As each interrupt is processed, it's source is disabled, to provide a cooling off period, after which each interrupt source is re-enabled. In general, interrupts should be few and far between for this module, I.e. link errors, timestamp synchronizing pulses, and halt triggers. Timestamp triggers are more problematic. There is only one timestamp interrupt enable bit, rather than one bit per channel. Each channel can be independently programmed, so that timestamp interrupts could come in close temporal proximity for two independent channels. On the other hand, if no "cooling off" period is enforced, a user could accidentally program this device to generate interrupts almost every usec. As a compromise, the timestamp interrupt is disabled for half the period of the other interrupts (~100 milliseconds). This will delay user notification of timestamp interrupt by up to this amount, but the timestamp itself will be correct (unless timestamps occur faster than 10 Hz for a particular channel).

  49. V124S Driver – bsTrigDrv.c – Code Review case BS_TRIG_CLOCK_MODE: if (arg) /* use internal reference */ BS_TRIG_REGISTER(pUserData->data->baseAddress, BS_TRIG_COMMAND_STATUS_REG, unsigned char) |= BS_TRIG_RF_CLK_SOURCE; else BS_TRIG_REGISTER(pUserData->data->baseAddress, BS_TRIG_COMMAND_STATUS_REG, unsigned char) &= ~BS_TRIG_RF_CLK_SOURCE; break; case BS_TRIG_SET_MODULE_MODE: if (arg) /* Enable the module */ BS_TRIG_REGISTER(pUserData->data->baseAddress, BS_TRIG_COMMAND_STATUS_REG, unsigned char) |= BS_TRIG_MODULE_ENABLE; else BS_TRIG_REGISTER(pUserData->data->baseAddress, BS_TRIG_COMMAND_STATUS_REG, unsigned char) &= ~BS_TRIG_MODULE_ENABLE; break;

  50. V124S EPICS Interface – Device Support • Device Support # EPICS Device Support for Beam SYNC Trigger Module device(longin,INST_IO,devLiBSTrigger,"BSTrigger") device(longin,INST_IO,devLiBSTriggerChan,"BSTriggerChan") device(longout,INST_IO,devLoBSTrigger,"BSTrigger") device(longout,INST_IO,devLoBSTriggerChan,"BSTriggerChan") device(bo,INST_IO,devBoBSTrigger,"BSTrigger") device(bo,INST_IO,devBoBSTriggerChan,"BSTriggerChan")

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