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Naming Conventions for Registers

0 $zero constant 0 (Hdware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves . . . (callee can clobber) 15 $t7. 16 $s0 callee saves . . . (caller can clobber) 23 $s7

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Naming Conventions for Registers

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  1. 0 $zero constant 0 (Hdware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8 temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hdware) Naming Conventions for Registers

  2. Review: MIPS ISA, so far

  3. Question I: Assume that memory has 232 addressable locations, and MIPS is 32-bit architecture. Please specify the width of the following address and data lines between the processor and the memory. read addr/ write addr Processor Addressable locations 232 read data Memory write data

  4. Question II: • Question 3.10 on page 199 (PH text book) • Question 3.5 on page 198 (PH text book)

  5. Question III: • What if the branch destination is further away than can be captured in 16 bits? What can the assembler do to alleviate this problem? beq $s0, $s1, L1

  6. Question IV: Give the machine code for the following assembly code segment: (you may use the combination of decimal, hexidecima, and/or binary encodings.) 0x00400040 Loop: add $t1, $s3, $s3 add $t1, $t1, $t1 add $t1, $t1, $s6 lw $t0, 0($t1) bne $t0, $s5, Exit add $s3, $s3, $s4 j Loop Exit:

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