HCC Reset Scheme

1. HCC Reset Scheme

2. Sources of Reset • “Hard” reset • Any one of 4 separate sets of reset blocks • SYS Reset • Short command • Soft Reset • Short command • ePll reset • “Register Write” HCC Reset Scheme

3. Hard Reset • Left/Right reset pad (active low) • Pull ups, so we AND these two lines • Power up reset (active low) • From ABC130 • Prompt circuit (active high) • Radiation detection, 3 cells, AND’ed • Inverted when combined with the others • Trigger generated reset • 32 consecutive L1, R3 triggers HCC Reset Scheme

4. Hard Reset (2) • These 4 sources are AND’ed together • hardRstb • Left/Right ResetXOR pad • Pull ups, AND’ed together • Inverted so normal state is 0 • resetXOR • xorHardRstb = resetXOR XOR hardRstb HCC Reset Scheme

5. Hard Reset (3) • xorHardRstb resets: • Demultiplexers for L0_CMD and R3_L1 • Command Decoder HCC Reset Scheme

6. SYS Reset • Resets logic blocks • Does not reset: • Blocks reset by Hard Reset • Registers • ePll HCC Reset Scheme

7. Soft Reset • Nearly full chip reset • Does not reset: • Blocks reset with Hard Reset • ePll HCC Reset Scheme

8. ePll Reset • HCC specific, long command • Look like register write • Generate a “long” (~few us) reset pulse • It is expected that a SYS Reset will be required HCC Reset Scheme