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Design and Implementation of VLSI Systems (EN0160)

Design and Implementation of VLSI Systems (EN0160) Lecture 17: Static Combinational Circuit Design (1/2). Prof. Sherief Reda Division of Engineering, Brown University Spring 2007. [sources: Weste/Addison Wesley – Rabaey/Pearson].

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Design and Implementation of VLSI Systems (EN0160)

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  1. Design and Implementation of VLSI Systems (EN0160) Lecture 17: Static Combinational Circuit Design (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. Sketch a 2 by 1 multiplexer design using AND, OR, and NOT gates. How to convert an AND/OR to a NAND/NOR network?

  3. Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan’s Law Converting AND/OR networks to NAND/NOR networks

  4. Logical Effort of compound gates Compound gates

  5. The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. Delay calculation example H = 160 / 16 = 10 B = 1 N = 2

  6. Solution: simple versus compound for the MUX case

  7. Annotating design with transistor sizes • Annotate your designs with transistor sizes that achieve this delay.

  8. Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2t If B arrives latest? 2.33t Parasitic modeling • If input arrival time is known • Connect latest input to inner terminal

  9. Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same gA = gB = gtotal = gA + gB = Asymmetric gate approaches g = 1 on critical input But total logical effort goes up Asymmetric gates • Asymmetric gates favor one input over another • Ex: suppose input A of a NAND gate is most critical • Use smaller transistor on A (less capacitance) • Boost size of noncritical input • So total resistance is same • gA = 10/9 • gB = 2 • gtotal = gA + gB = 28/9 • Asymmetric gate approaches g = 1 on critical input • But total logical effort goes up

  10. Inputs can be made perfectly symmetric Symmetric gates

  11. Skewed gates favor one edge over another Ex: suppose rising output of inverter is most critical Downsize noncritical nMOS transistor Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. gu = 2.5 / 3 = 5/6 gd = 2.5 / 1.5 = 5/3 Skewed gates

  12. Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction But larger for the other direction Hi- and Lo-Skew

  13. Catalog of skewed gates

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