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Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) PowerPoint Presentation
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Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2)
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  1. Design and Implementation of VLSI Systems (EN0160) Lecture 11: Logical Effort (1/2) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

  2. Last lecture: delay estimation We calculated Rise and Fall delays Q: What happens if we decide to scale the transistors by factor k?

  3. Impact of transistor sizing What happens to delay? Is it the case that increasing the size of the transistor always reduces delay?

  4. Impact of sizing in a path ×K Cout Less output resistance; increase output capacitance → delay reduces (parasitic delay stays the same) Larger input capacitance → increases delay of previous stage! What is the final outcome? Should we size? By how much?

  5. If you decide to increase everything by a factor of k Unloaded delay =3RC  12 ps in 180 nm process 40 ps in 0.6 mm process Remember gate design How about an inverter?

  6. “normalized delay” Expressing delay as a linear model

  7. Summary of linear delay model • g: logical effort= ratio between input capacitance of the gate size to the input capacitance of theinverter that would deliver the same current • h: electric effort = ratio between load capacitance and the gate input capacitance (sometimes called fanout) • p: parasitic delay • represents delay of gate driving no load • set by internal parasitic capacitance

  8. Computing logical effort

  9. Computing parasitic delay

  10. Estimate the frequency of an N-stage ring oscillator Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Frequency: fosc = Example: Ring oscillator

  11. Example: Ring oscillator • Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: fosc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 mm process has frequency of ~ 200 MHz

  12. Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = Electrical Effort: h = Parasitic Delay: p = Stage Delay: d = Example: FO4 Inverter

  13. Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 Example: FO4 Inverter The FO4 delay is about 200 ps in 0.6 mm process 60 ps in a 180 nm process f/3 ns in an fmm process