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Design and Implementation of VLSI Systems (EN0160)

Design and Implementation of VLSI Systems (EN0160). Sherief Reda Division of Engineering, Brown University Spring 2007. [sources: Weste/Addison Wesley – Rabaey Pearson]. Last time Gate layouts and stick diagrams This time MOS transistor theory (ideal case).

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Design and Implementation of VLSI Systems (EN0160)

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  1. Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey Pearson]

  2. Last time Gate layouts and stick diagrams This time MOS transistor theory (ideal case) Lecture05: MOS transistor theory

  3. gate-oxide-body sandwich = capacitor • Operating modes • Accumulation • Depletion • Inversion • The charge accumulated is proportional to the excess gate-channel voltage (Vgc-Vt)

  4. Cut off Vgs < Vt • Linear (resistor): Vgs > Vt & Vds < Vgs-Vt NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V Current α Vds • Saturation: Vgs > Vt and Vds ≥ Vgs-Vt Current is independent of Vds The MOS transistor has three regions of operation

  5. MOS structure looks like parallel plate capacitor while operating in inversion Gate – oxide – channel Qchannel = CV C = εoxWL/tox = CoxWL (where Cox=εox/tox) V = Vgc – Vt = (Vgs – Vds/2) – Vt How to calculate the current value?

  6. Charge is carried by electrons Carrier velocity v proportional to lateral E-field between source and drain v = μE μ called mobility E = Vds/L Time for carrier to cross channel: t = L / v Carrier velocity is a factor in determining the current

  7. Now we know How much charge Qchannel is in the channel How much time t each carrier takes to cross I=Q/t

  8. Can be ignored for small Vds In linear mode (Vgs > Vt & Vds < Vgs-Vt) • For a given Vgs, Ids is proportional (linear) to Vds

  9. In saturation mode (Vgs > Vt and Vds ≥ Vgs-Vt) • Now drain voltage no longer increases current

  10. Operation modes summary • 0.6 micron process • tox = 100 Å • m = 350 cm2/V*s • Vt = 0.7 V • W/L = 4/2 l

  11. PMOS is similar

  12. What happens when we construct a INV (PMOS+NMOS)?

  13. Inverter voltage transfer function A B C E D

  14. This lecture Ideal transistor modeling Next lecture Non ideal transistor modeling Summary

  15. Inverter current transfer function

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