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Data processor description, development plan and risk analysis

Data processor description, development plan and risk analysis. Giuseppe Osteria INFN Napoli. Giuseppe Osteria INFN Sezione di Napoli. Toulouse, February 2, 2012. Euso Balloon Phase A Review. Data Processor component. List of Subsystem of EUSO Balloon.

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Data processor description, development plan and risk analysis

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  1. Data processor description, development plan and risk analysis Giuseppe Osteria INFN Napoli Giuseppe Osteria INFN Sezione di Napoli Toulouse, February 2, 2012 Euso Balloon Phase A Review

  2. Data Processor component List of Subsystem of EUSO Balloon List of the components for every subsystem

  3. Data Processor component

  4. Data Processor:Functional requirements The DP system main functions: • controlling and configuring the front-end electronics • performing the second level trigger filtering • tagging events with arrival time (UTC) and payload position (GPS) • providing Mass Memory (Data Storage system) for on board data storage • managing the Data Storage system • measuring live and dead time of the instrument • providing signals for time synchronization of the event • performing housekeeping monitor • handling interface to tele-commands and to telemetry system. • controlling the IR camera (adv. option)

  5. Data processor:Subassembly items The DP functionality is obtained by connecting different specialized items, which form a complex system. The main subassembly items are: • Control Cluster Board (CCB) • Main processing unit (CPU) • Data Storage (DST) • Housekeeping system (HK) • Clock Board (CLKB) • GPS receiver (GPSR) • Data Processor Power Supply (DP-LVPS)

  6. Data Processor: Block diagram DP LVPS 28V V, A Monitor v 12V 28V HK system SIREN system HL-CMD CPU RS232 v V, T monitor RS232 5V 5V CCB v SpaceWire to GbE/ PCI SpaceWire v 12V, 5V, 3.3V Data Storage Analog (V, T) Data Storage v SATA CLKs,Sync, Trig Gbit-Ether. or PCI v 5V CLK board v SpaceWire I2C or SPI Visible cam (adv. opt.) Fast parallel link v USB v RS232 3.3V GPS v USB? PDM box IR Camera (adv. opt.) PWP SpaceWire?

  7. Data processor subassembly – CCB -Functional requirements: The Cluster Control Board has to • Interface with CLKB • Receiving the clock and Synchronization signal • Sending the 2nd level trigger • Interface with PDM subsystem • Passing the clock signals from the clock distribution board to PDM • Passing the configuration data from CPU to PDM • Transferring data from PDM over a fast parallel data link after receiving a 1st level trigger • Performing the 2nd-level trigger analysis on the PDM triggered data. • The trigger algorithm implemented is the JEM EUSO Linear Track Trigger (LTT) tailored on the EUSO-Balloon configuration. The LTT searches, in a set of 67 (TBD) predefined directions, for tracks developing at the speed of light. As result of the trigger analysis the data will be classified as data to be: • stored on board • sent via SIREN to ground • stored and sent to ground • erased • Notify the CPU about the decision • Transfer the data via SpaceWire to the CPU (for priorities 1-3) or simply discard the data without notification for priority 4.) • Interface with HKDP for analog sensors

  8. Data processor subassembly – CCB - Maturity, development status: • IAAT has recently completed the development of a prototype of the JEM-EUSO CCB-Board. • The JEM-EUSO CCB-Board has to manage 9 PDMs so is by far more complex than the one foreseen for the EUSO-Balloon • Most of required functionality of the EUSO-Balloon CCB PFM has been implemented on Proto model • The JEM-EUSO CCB-Board can be considered as a Proto model of the EUSO-Balloon CCB unit. Laboratory prototype of JEM EUSO CCB

  9. Data processor subassembly – CCB -Description: • Board based on an FPGA Xilinx Virtex4 FX60 (Industrial grade). All the required functionalitiesof the board will be implemented on the FPGA. • An external 4Mbit SRAM will store the events while processing the data. • The hardware architecture is highly pipelined and parallelized in order to perform the necessary calculations as fast as possible • The CCB FPGA will host the following interfaces: • Fast bidirectional parallel data interface with LVDS to PDM • Gain Reduction signal from PDM • 400kHz GTU clock from Clock Board to PDM • 40MHz system clock from Clock Board to PDM • Time-Sync Signal from Clock Board • Command and data interface from/to the CPU via Space Wire • Analogue sensors to HK • Formfactor: 3U Euro card (160 mm x100 mm x 25 mm ) The block diagram of the CCB board

  10. Data processor subassembly – CCB -Development plan • Design of PFM will start at IAAT after the review of mechanics and electrical interfaces (in progress) • Development of the VHDL code already started • PCB design will completed at the end of March 2012. • Proto Flight Model will be ready to be tested by mid-October 2012. • To test the CCB board a specific TEST-CCB board will be also developed. IAAT is developing a PDM board simulator and interfaces with a “testing” near real time framework. Extensive testing and debugging reduces risks. • Testing shall be completed, under planned circumstances, by mid-December 2012 (with a good margin).

  11. Data processor subassembly – CPU -Functional requirements: The CPU has to: • manage the acquisition of science data from the instrument; • manage the Data Storage in order to store science and telemetry data received from the instrument and the on board sensors and transducers; • manage communication with the SIREN system to transmit data to ground and receive tele-commands; • prepare and broadcast control commands to the instrument; • control the HK board and collect HK data; • control the IF camera and collect IF camera data (adv. Opt.); • control the Visible camera and collect Visible camera data (adv. Opt.).

  12. Data processor subassembly – CPU -Maturity, development status: The CPU will be Commercially available Off-The-Shelf (COTS) component Two candidates have been selected: • Arbor ITX-i2705 board based on Intel Atom Processor N270 (1.60 GHz) 2 SATA ports, RAID 0, 1 supported • Power consumption 12 W • Operating temperature -20° C to +70° C • Eurotech Antares Core i7 EBX board. 5.25” Single board Computer based on Intel Core i7 620UE 1.06GHz processor • 4 SATA ports, RAID 0, 1, 5 supported • Power consumption 18-25 W • Operating temperature -20° C to +60° C • The two boards (already ordered) will be tested and their performance will be compared. After the comparison one system will be selected and will be considered the proto model of the EUSO-Balloon CPU. (end of May 2012) • If the proto model of the EUSO-Balloon CPU would fulfill all the requirements then it will be considered the PFM of the CPU. The Arbor board The Antares board

  13. Data processor subassembly – CPU -Description: • The CPU receives science data from the Control Cluster board and from the CLK board. • According to the classification operated by CCB board the CPU will decide, for each event, if data will be • stored on board, • transmitted to ground via Siren board • both. • The CPU archives data with a rate greater than the 200 Mbits/sec of the SpaceWire input stream. A fast transfer rate is highly recommended in order to increase the fraction of live time of the apparatus. • The amount of data produced by the apparatus for each event is of about 330 Kbyte. In a ten hours flight the total amount of data would easily overcome the 512 GB. Such a big amount of data will be handled by a robust (Real Time) Operating System (Linux, QNX, VxWork) with an adequate File system. A minimum of two SATA ports will guarantee the required data transfer rate. • The CPU transmits a set of events via the SIREN module to ground in real time. The interface with the SIREN system will be developed according to the SIREN specification and the payload throughput requirements. • The CPU controls the HK system and transmits/receives housekeeping data to/from it by using a serial protocol and through a RS232/RS422 serial port.

  14. Data processor subassembly – CPU -Main technical specifications:

  15. Data processor subassembly – CPU -Development plane: • Both boards already ordered (delivering at INFN NA in two weeks) • The two systems will be tested in parallel (same OS) • Measurements of the performance on the handling of Data storage. • Measurements of the performance on the handling the SpaceWire –PCI interface. • Selection of one of the two systems • Definition of the operating modes and list of commands for each subassembly (already in progress) in order to start the CPU software development • Integration test with DP subassemblies will start as soon as they will be available (middle of December 2012) • Iterative tests will allow optimizing of the CPU software up to completion of AIP procedure.

  16. Data processor subassembly – DST -Functional requirements: The Data Storage has to: • record on board scientific and telemetry data • Requested storing capacity greater than 512 GB • Requested write performance ≥150 Mbyte/sec (SATA 1) • A disk fault-tolerant system is required in order to fulfil the Data level of redundancy. • DST shall operate in RAID (Redundant Array of Independent Disks) mode. RAID-1 level has to be supported. RAID-5 level shall be preferred.

  17. Data processor subassembly - DST-Maturity, development status: The DST will be Commercially available Off-The-Shelf (COTS) component • In the current baseline design the mass storage is composed by an array of two Solid-State Drive (SSD) operating in disks fault-tolerant mode RAID-1 (Redundant Array of Independent Disks). • The SSD selected device is the 960 GB OCZ Colossus Plus SATA II 3.5" SSD drive with a SATA II interface and certified of a sustained transfer rate up to 250 MB/sec . • An array configuration composed of three or four Solid-State disks operating in RAID-5 mode is possible only by using the EurotechAntares EBX CPU board.

  18. Data processor subassembly - DST-Description: 2 x 960 GB OCZ Colossus Plus SSD 960GB Max Performance Read: Up to 245 MB/s Write: Up to 250 MB/s Max 4k Write IOPS: 12,300

  19. Data processor subassembly – DST -Development plan: • Two SSD drives model 960 GB OCZ Colossus Plus SATA II 3.5“ already ordered • They will be delivered in one month to INFN-Napoli • Once delivered the disks will be installed on the CPU and measurement of the performance will be done on both the CPU boards. • Testing shall be completed by the end March 2012

  20. Data processor subassembly – CLKB -Functional requirements: The Clock Board has to: • Generate and distribute • system clock (40 MHz) • GTU clock (400 KHz 98% duty cycle) • Tag the events with arrival time (UTC) and payload position (GPS) • Interfacing with a GPS system • Provide signals for time synchronization of the events • Measure live and dead time of the instrument • Transmit data to CPU and receive commands from CPU (SpaceWire interface) • Transmit board’s monitored parameters to HK (analog or via a serial protocol)

  21. Data processor subassembly – CLKB -Maturity, development status: A prototype of the CLKB has been realized at INFN-Na by using a Virtex5 evaluation board (ml505). The evaluation board mounts the same FPGA (Virtex5 XC5VLX50T) selected for the Proto Flight Model of the EUSO Balloon CLKB Most of required functionality of the EUSO Balloon CLKB has been implemented and successfully tested on the proto model: • clock generation, 40 MHz and 400 KHz (98% duty cycle) OK! • RS232 interface with GPS device (NMEA protocol) OK! • 1PPS GPS time interface OK! • GTU counters for synchronization OK! • dead and live time counters OK! • data strobe interface (OK but not full SpaceWire) This prototype can be considered a proto model of the CLKB ML505 Evaluation Platform

  22. Data processor subassembly – CLKB -Description: • An FPGA Xilinx Virtex5 XC5VLX50T (Industrial grade) will be used to implement all the required functionalities of the board. • Master clock: • 40 MHz Temperature Compensated Crystal Oscillator • frequency stability of +/-1 ppm in the temperature range of -40°C to +85°C. • The clock signals are transmitted to the CCB by using differential LVDS point-to-point connections. • The FPGA will host the following interfaces to: • GPS receiver through a RS232 port (NMEA protocol). • 1PPS pulse of the GPS receiver in order to synchronize, at level of 1 GTU, the apparatus with the UTC time. • CPU (Command and data interface via Space Wire) • HK (HK parameters: analog or via I2C or SPI serial protocol TBD) • Form factor: 3U Euro card (160 mm x100 mm x 25 mm )

  23. Data processor subassembly – CLKB -Development plane • Design of the CLKB almost completed at INFN of Naples (review of mechanics and electrical interfaces still in progress) • PCB design will be completed by the end of March 2012 • Development of the VHDL code already started (first validation of the code on the ml 505 evaluation board) • CLKB Proto Flight Model will be ready to be tested by the middle of October 2012 • Integration and test of the interfaces with GPS system once it will be available) • Validation of the Space Wire interface with GRESB SpaceWire/Ethernet Bridge manufactured by AeroflexGaissler. • Testing shall be completed, under planned circumstances, by the end of December 2012.

  24. Data processor subassembly – GPSR –Functional requirements: The GPS receiver has to: • provide the UTC time and the position of the payload during the flight. • provide correct data and signals from ground up to 42 km above sea level. (No ITAR restriction) • provide the UTC time with an accuracy of 1 µs. • make available (in order to be properly interfaced by the CLK board): • A 1PPS output • A RS232 data/command communication port (NMEA protocol) • The GPS receiver shall provide the position of the payload with an accuracy of 10 m (TBC)

  25. Data processor subassembly – GPSR –Maturity, development status: • The GPSR will be a Commercially available Off-The-Shelf (COTS) component • several GPS receiver are available on the market which are sold with an optional firmware allowing the device to properly work at high altitude. • Other devices, available from non U.S. manufacturers are also under investigation.

  26. Data processor subassembly – GPSR –Description: • A possible GPSR candidate is based on the SiRFstarIII™ 20-channel GPS SMD compact module/receiver • The ISM300F2-C5-V0004 module is programmed with HIGH ALTITUDE BUILD, and works at cold temperatures for ballon applications. • Maximum altitude of 42000 meters (137795 ft) • Avalaible interfaces: • SiRF Binary at 57600 baud on port A • NMEA at 4800 baud on port B • 1 PPS output • ITAR-free component

  27. Data processor subassembly – GPSR –Development plane: • The GPS receiver will be ordered at mid of July • It will be delivered in one month to INFN-Na. • The interface between GPS receiver and CLK board will be tested as soon as the receiver will be delivered. The test will be performed by using the Virtex5 evaluation board ml505 and, once it will be available, the flight model of the CLK board. • Testing shall be completed by the end October 2012

  28. Data processor subassembly – HKDB -Functional requirements: The HouseKeeping Board has to • distribute tele-commands • collect telemetry from several sub-systems of the instrument and to generate alarms. • interface with SIREN for On/Off (HL_Cmd) • Interface with PDM-LVPS and DP-LVPS for status verification (CC) and voltage and current monitoring • communicate with CPU for tele-command and telemetry • receive analog signals from CCB, PDM, FL, SL and TL for sensors • be able to turn On/Off and verify the status of any other sub-system that might be required through HL Cmd & CC. The HKDP operates in slow control mode, i.e., within time scales of the order of 1 to few seconds.

  29. Data processor subassembly – HKDB -Maturity, development status: • The HKDB will consist of an off-the-shelf component (a microprocessor board) and a stack of child boards for power supply, signal conditioning, multiplexing, communication protocol implementation and connectors • The design of the child boards will be a brand new design • Proto model of the child boards will be designed and manufactures at UNAM • Assembly, integration and test of the proto model child boards with the microprocessor board will be performed prior to production of the HKDP Flight Model.

  30. Data processor subassembly – HKDB -Description: • the HKDP will be implemented around a microprocessor board, Arduino Mega 2560, combined with protocol interface boards to pre-process the various signals. • The Arduino Mega 2560 is a microcontroller board based on the ATmega2560. It has 54 digital input/output pins with 14 of them allowing PWM outputs, an additional 16 analog inputs, 4 UARTs (hardware serial ports), and an USB connection. • The interface boards will perform signal conditioning, multiplexing and will host communication busses. Between 2 and 5 boards will be stacked together to conform a HKB assembly depending on the final number of interfaces to be managed. • The HKDP functions in two modes: cyclic and on-demand from the CPU or ground through SIREN.

  31. Data processor subassembly – HKDB -Development plan: • Test of the Arduino board in the environmental EUSO-balloon operating conditions (Pressure and Temperature)will be done in the next month in order to validate the current strategy. • Design of the proto model of the child boards in progress (review of the interfaces) • A testing bench is already being design to simulate the serial communication with different sub-systems and the reception, conditioning and processing of analog signals from sensors. • The HL_CMD for On/Off and CC for status verification, as well as monitoring of current and voltages from the LVPS boards have already been extensively simulated and validated experimentally. • The Flight model of HKDP will be ready to be tested by the mid-November 2012 • Testing shall be completed, under planned circumstances, by the end of December 2012.

  32. Data processor subassembly - DP-LVPS -Functional requirements: The DP-Low Voltage Power Supply has to: • distribute power in an efficient and reliable way to the CPU, CCB, GPS, CLK and DST. • provide isolation interface between the 28V bus PWP and the DP subassemblies • interface SIREN and/or HKDP for On/Off (HL_Cmd), • Interface with HKDP for status verification (CC) and voltage and current monitoring

  33. Data processor subassembly - DP-LVPS - Maturity, development status: • UNAM has already produced a prototype of JEM-EUSO PDM-LVPS which is very similar to the EUSO-Balloon PDM-LVPS and DP-LVPS • The JEM-EUSO PDM-LVPS prototype can be considered a proto model of the EUSO-Balloon DP-LVPS • The JEM-EUSO PDM-LVPS prototype has been already extensively tested with static and dynamic loads • Slightly modified versions of this board will be redesigned and built with the philosophy of PFM A laboratory prototype of the JEM-EUSO PDM-LVPS.

  34. Data processor subassembly - DP-LVPS - Description: • The DP-LVPS board is divided in 3 main sections: • 4 voltage converters, fed with a nominal voltage equal to 28 V, supplying 3.3V, 5 V, 12 V and 5 V auxiliary, • The DC/DC converters actually considered belong to the UEI15 series manufactured by Murata PS. • Interface to the High-Level Command (HL_Cmd) • The PSB latching relay receives two High-Level Commands (HL_cmd’s) from either PWS, CPU or HKDP (TBD) • Voltage and current monitoring circuitries supplying 3.3V, 5 V and 12V. • A 5 V auxiliary converter polarizes the voltage and current monitoring circuitries which provide floating signals to the HKDP via a DB-15 connector.

  35. Data processor subassembly - DP-LVPS - Development plan: • Design of the DP-LVPS almost complete • A PFM should be finished by June 2012 and there is enough contingency time to produce a revised board in case it were necessary to implement modifications for the FM. • Preliminary tests will be performed with a dynamical load simulator already built at UNAM, and later together with the PDM board, the CPU and the CCB teams.

  36. Data Processor: Budgets • Size: DP will be housed in a customized Eurocard 6U subrack with 3U dividers (baseline option) • Mass: DP mass is estimated to be about 5 Kg • Power budget: DP power budget is estimated to be 45 W 6U Subrack with 3U Dividers.

  37. Data Processor: Risk analisys summary • Risk for the development and implementation phase: • Procurements • No criticality for key elements (no ITAR components) • Developments • good maturity for each subassembly (COTS components or systems with proto model already produced) • Implementation • Complex system with many interfaces • (DP System manager + cooperative and harmonic collaboration among involved teams) • Interface with Nosyca system • (Nosyca is now sufficiently close to the delivery) • Schedule • good margins for each subassembly • Risk for Launch/Flight/Recovery phase • Failure of electronic subsystem during flight • Overheating/ electronics leading to failure • (Thermal study foreseen, Test of subassemblies in vacuum test chamber if needed)

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