Circuit Retiming with XOR Gates

1. Retiming

2. XOR XOR XOR Consider the Following Circuit • Suppose TXOR = 3 ns, Tpcq = 1 ns, Tsetup = 1 ns, then this circuit can be clocked at 1 ns + (3 x 3 ns) + 1 ns = 11 ns. D-FF D-FF X D-FF Y F D-FF Z

3. XOR XOR XOR XOR XOR XOR Why Are They Not Equivalent? • Suppose FFs are initialized to 0 D-FF D-FF P D-FF D-FF D-FF X X D-FF D-FF Y Y F F D-FF D-FF Z Z 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 F 0 1 0 1 F 0 0 1 1 X 1 1 1 1 X 1 1 1 1 Y 1 1 1 1 Y 1 1 1 1 Z 1 1 1 1 Z 1 1 1 1

4. XOR XOR XOR XOR XOR XOR Are These Equivalent? • Suppose FFs are initialized to 0 1 fewer D-FF But same delay D-FF P D-FF D-FF X X D-FF D-FF Y Y F F D-FF D-FF Z Z 0 1 0 1 0 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 F 0 1 0 1 F 0 1 0 1 X 1 1 1 1 X 1 1 1 1 Y 1 1 1 1 Y 1 1 1 1 Z 1 1 1 1 Z 1 1 1 1

5. Basic Idea of Retiming • If you have 2 FFs at the inputs, you can move it to the output • Or if you have a FF at the output, you can move it to the inputs • In general, can move N FFs from inputs to output, and vice versa D-FF X X D-FF F F D-FF Y Y

6. XOR XOR XOR Example • How to move FFs around to minimize clock period? (assuming Tpcq = Tsetup = 0)

7. Graph Model 0 0 3 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 • Vertex vi, combinational node, delay = d(vi) • All inputs and outputs connect through a faux node “host” with d(host) = 0 • Edge e(vi, vj) or eij, weight wij = number of flip-flops between vi and vj

8. Path Delay and Path Weight • A set of connected nodes specify a path • Path delay = ∑ d(vi) = comb. delay of path • Path weight = ∑ wij = # FFs along the path • Retiming of a node i denoted by an integer ri • It represents the number of registers moved across, initially ri = 0 • Register moved from output to input, ri → ri + 1 • Register moved from input to output, ri → ri – 1 • After retiming, edge weight wij’ = wij + rj – ri

9. Example Critical path delay = 10 f g e 0 0 3 3 3 r(e)=0 0 r(f)=0 r(g)=0 0 0 0 0 0 h r(h)=0 1 1 1 1 1 1 1 1 a r(a)= 0 r(b)=0 r(c)=0 r(d)=0 c b d Initial retiming vector = {0,0,0,0,0,0,0,0}

10. Retimed Example Critical path delay = 5 f g e 0→1 0→1 3 3 3 r(e)= –2 0 r(f)= –1 r(g)=0 0 0 0 0→1 0 h r(h)=0 1→0 1→0 1 1 1 1 1 1 a r(a)= –1 r(b)= – 1 r(c)= –2 r(d)= –2 c b d Optimal retiming vector = {-1,-1,-2,-2,-2,-1,0,0}

11. XOR XOR XOR Optimized Circuit

12. Retiming Theorem • Given a network G(V, E) and a cycle time T, (r1, r2, . . . ) is a feasible retiming if and only if:ri – rj ≤ wij for all edgesri – rj ≤ W(vi, vj) – 1 for all node-pairs (vi, vj) such that D(vi, vj) > TwhereW(vi, vj) is the minimum weight path between vi and vjD(vi, vj) is the maximum delay among all minimum weight paths between vi and vj. • Above is a Linear Program, which can tested for feasibility for a given T. • Binary search over possible cycle time T.

13. Retiming & Resynthesis

14. Initial State • What should be the new initial state? 0 X X 0 F F 0 Y Y

15. Cannot Always Recover Initial State • Cannot always get exactly the same initial state behavior on the retimed circuit • For some applications, a startup transient may not be a problem 1 0 1 1 1 ? 1 1 0 1 1 1