Integrating Logic Retiming and Register Placement

1. Integrating Logic Retiming and Register Placement Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay Yih-Chih Chou, and Youn-Long Lin Department of Computer Science Tsing Hua University Hsin-Chu, Taiwan, R.O.C.

2. Outline • Motivation • Key problems • Proposed System flow • Retiming algorithm • Interconnection delay estimation • Register placement • Experimental results • Conclusion and future work

3. gate delay retiming wiring delay layout Motivation • Wiring delay dominance in VDSM era. • Retiming cannot ignore wiring delay. • Wiring delay is layout dependent. ? ?

4. Key Problems • Post-Layout Retiming incorporating interconnection delay • Interconnection delay estimation • delay change due to register insertion or removal • tree topology dependence • Post-retiming (register) placement

5. Retiming Incorporating Interconnection Delay • Given estimated interconnection delay, find a legal retiming such that the clock period of the circuit is optimal. a b c Delays a, b, and c must be estimated before retiming.

6. Previous Work • Soyata and Friedman (ICCAD’94): • branch-and-bound method • optimal solution in the first time • time consuming • Lalgudi and Papaefthymiou (DAC’95): • integer linear programming method • optimal solution • polynomial time algorithm if the circuit is one-way extendible

7. Interconnection Delay Estimation • Given layout • Estimate wiring delay change due to register insertion or removal • Tree-topology dependence of wiring delay

8. Effect of Register Insertion or Removal on Wiring Delay (a) adding a register (b) deleting a register (c) an unchanged wire

9. Tree-Topology-Dependence of Wiring Delay

10. Post-Retiming (Register) Placement • Post-retiming layout refinement to meet timing goal • Need specific technique

11. Proposed System Flow

12. Retiming Incorporating Wiring Delay • Extend a previous algorithm (proposed in pp.384-393, SASIMI’93) to incorporate the interconnection delay. • Efficient, optimal for circuits satisfy the path monotonicity constraints.

13. Interconnection Delay Estimation (a) adding a register (b) deleting a register (c) an unchanged wire

14. In the slot nearest the geometric center among its fan-in and fan-out cells. G42709 G40392 G42767 Predicting Location for the Inserted Register

15. Tree-Topology Selection • Choosing the one with the most delay.

16. Post-Retiming (Register) Placement • Freeze all combinational cells • Relocate all registers in 3 steps • Slack assignment • Placement range calculation • Simultaneous register to slot assignment

17. Slack Assignment

18. Placement Range 0.172 0.215 G42612 G40391 0.110 G42552

19. Simultaneous Register Place-ment by Bipartite Matching G161 G164 G170 G167 G173 G170 G176 G173 G180 slot register G176 G183 G180 G188 G183 G191 G188 G218 G191 G194

20. Experimental Results

21. Conclusion • Retiming and layout are combined for the first time. • Three sub-problems: retiming incorporating interconnection delay, delay estimation, and post-retiming (register) placement.

22. Future Work • Tightly coupled simultaneous placement and retiming • Retiming considering wire delay and number of registers • Using more advanced delay model and considering more VDSM effects