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LDO characterization

LDO characterization. Laura Gonella Physikalisches Institut Uni Bonn. Status. Tests performed on the LDO mode of the Shunt-LDO regulator Single device characterization Line regulation (*) T dependence Load regulation (*) T dependence Load transient

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LDO characterization

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  1. LDO characterization Laura Gonella Physikalisches Institut Uni Bonn

  2. Status • Tests performed on the LDO mode of the Shunt-LDO regulator • Single device characterization • Line regulation(*) • T dependence • Load regulation(*) • T dependence • Load transient • Parallel operation: same Vin, different Vout • Line regulation • Load regulation • Load transient (*) These results have already been shown and discussed. They are added here as useful material for the design review

  3. Single device characterization • Both regulators on chip have been tested independently • Results are in good agreement • Shown here results from Reg2

  4. Line regulation • For a certain Iload, the Vout is stable as a function of Vin, once the output is regulated • To have a regulated output up to Iload = 600mA the Vdrop has to be at least 200mV • Even ~270mA for Iload = 600mA and Vout = 1.2V • The lower Vout for Iload = 0.6A is due to the bad load regulation

  5. Line regulation: T dependence • The line regulation is stable in a T range from +20°C to -20°C

  6. Load regulation • For Iload<10mA, the output stage of the amplifier A1 that controls the pass transistor is driven out of saturation which decreases the regulation loop gain. This explains the bad load regulation for Iload < 10mA • Investigations are ongoing to explain the bad load regulation for Iload > 10mA • The test setup seems to be fine • Results on 4 chips from 2 different wafers agree, excluding process variation • Simulations with corners and T are good • Ongoing post layout simulations with extracted parasitics to extimate the on chip wiring resistance

  7. Load regulation

  8. Load regulation: T dependence • The load regulation is stable in a T range from +20°C to -20°C

  9. Load transient • Vout = 1.2V, Vin = 1.9V • Need to have Vin high enough to make sure Vdrop is >200mV during the transient • Load current pulse measured across a 100mΩ resistor • Iload = 66mA → 190mA, ΔIload = 124mV • Rise time = fall time = 200ns • Pulse width = 10us • ΔVout = 18.0mV • Rout = 145mΩ

  10. Load transient • Vout = 1.5V, Vin = 2.0V • Need to have Vin high enough to make sure Vdrop is >200mV during the transient • Load current pulse measured across a 100mΩ resistor • Iload = 98mA → 330mA, ΔIload = 232mV • Rise time = fall time = 200ns • Pulse width = 10us • ΔVout = 29.2mV • Rout = 126mΩ

  11. Load transient • This is what happens if Vin is not high enough • Same as previous slide, just with Vin = 1.9V

  12. Parallel operation • Reg1 generates Vout = 1.5V • Reg2 generates Vout = 1.2V • The Vin is in common • The Vdrop on the Vin lines (from supply to the chip pad) is slightly different so Vin1 ≠ Vin2 • Reg2 sees a Vdrop ≥ 0.4V

  13. Line regulation • Iload1 = 380mA • Iload2 = 180mA

  14. Load regulation • Iload2 = 180mA, Vout = 1.169V • Iload1 = 0 – 0.6A

  15. Load regulation • Iload1 = 380mA, Vout = 1.446V • Iload2 = 0 – 0.6A

  16. Load transient • Iload1 = 380mV • Iload2 = 58mA → 184mA, ΔIload = 126mV; rise time = fall time = 200ns; pulse width = 10us Vin2 Vout2 Vin1 Vout1 • ΔVout2 = 17.2mV • Rout2 = 137mΩ • ΔVin2 = 350mV • ΔVin1 = 320mV • ΔVout1 = 6mV

  17. Load transient • Iload2 = 180mV • Iload1 = 114mA → 348mA, ΔIload = 234mV; rise time = fall time = 200ns; pulse width = 10us Vin1 Vout1 Vin2 Vout2 • ΔVout1 = 30.8mV • Rout1 = 132mΩ • ΔVin1 = 650mV • ΔVin2 = 590mV • ΔVout2 = 4.8mV

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