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Dezső Sima Fall 2007

Systemarchitecture. Dezső Sima Fall 2007. (Ver. 2.1).  Sima Dezső, 2007. Contents. 1. Introduction to system architectures. 2 . The evolution of the system architecture. 3 . The evolution of Intel’s x86 processor bus. 4. Bus innovations introduced in Intel’s P4 chipsets.

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Dezső Sima Fall 2007

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  1. Systemarchitecture Dezső Sima Fall 2007 (Ver. 2.1)  SimaDezső, 2007

  2. Contents 1. Introduction to system architectures 2. The evolution of the system architecture 3. The evolution of Intel’s x86 processor bus 4. Bus innovations introduced in Intel’s P4 chipsets 5. Chipsets of Intel’s P4 family 6. Bandwidth considerations 7. Special aspects of the implementation

  3. 1. Introduction to system architectures

  4. 1. Introduction Pentium Pro Processor Concrete architecture Pentium Prosystem Abstract architecture OS System level Pentium Pro ISA Processor level FMUL Functional unit level Figure 1.1.: Interpretation of the notion architecture at different levels

  5. 2. The evolution of the system architecture

  6. 2. The evolution of the system architecture 2.1 System architecture of Intel’s desktop PCs - Overview System architecture of Intel’s desktop PCs ISA-based Port-based PCI-based w/ATA, USB Simple w/AGP,ATA,USB Early implem. Recentimplem. 8088/80286/80386-based PCs 486 and early Pentium based PCs Mature Pentium based PCs Early PII and PIII based PCs Mature PIII/P4 based PCs P4 Prescott based PCs Mature Intel 430 chipsets Intel 440XX chipsets Intel 8XX chipsets Intel 915X chipsets Intel 420 chipsets Evolution

  7. 2.2 Main steps of the evolution (1) 8088/80286/80386 Processor Monitor WD FD PP SP Adapter Adapter Adapter Adapter Adapter Memory/ Main Memory KBD Bus controller (DRAM/FPM) ISA Multi-I/O card I/O devices Figure 2.1: ISA-bus based system architecture (Used typically in 8088/80286/80386-based PCs)

  8. 2.2 Main steps of the evolution (2) L2 cache Peripheral controller 486/Pentium Processor bus System Main Memory (FPM/EDO) controller PCI bus PCI device adapter ISA bus (Legacy and/or ISA device adapter slow devices) Figure 2.2: Simple PCI-based system architecture (Used typically in 486 and early Pentium-based PCsalong with Intel 420 and early 430 chipsets)

  9. 2.2 Main steps of the evolution (3) Pentium L2 cache PCI device adapter ISA device adapter Processor bus System Main Memory controller (FPM/EDO/SDRAM) PCI bus IDE/(ATA/33) IDE port: First on the 430FX (Triton, 1995) ATA/33: First on the 430TX (1997) USB: First on the 430VX (Triton III, 1996) Peripheral controller USB ISA bus (Legacy and/or slow devices) Figure 2.3: PCI-based system architecture with IDE/ATA and USB ports (Used typically in mature Pentium-based PCs with mature Intel 430 chipsets)

  10. 2.2 Main steps of the evolution (4) PentiumII/ PentiumII/ PentiumIII PentiumIII PCI device adapter ISA device adapter Processor bus System Main Memory AGP (EDO/SDRAM) controller PCI bus (Legacy and/or 2xIDE/ATA33/66 slow devices) Peripheral controller 2xUSB ISA bus Figure 2.4: PCI-based system architecture with AGP, IDE/ATA and USB ports (Used typically in PentiumII and early PentiumIII-based PCs with Intel 440XX chipsets)

  11. 2.2 Main steps of the evolution (5) PentiumIII/ Pentiu4 PCI device adapter ISA device adapter Processor bus System Main Memory AGP (SDRAM/) controller Hub interface LPC 2xIDE/ (Used typically in PentiumIII and Pentium4-based systems with Intel 8X0 chipsets) ATA 33/66/100 Super I/O (KBD, MS, FD, SP, PP, IR) Peripheral controller AC'97 2x/4x USB PCI bus PCI to ISA bridge ISA bus (Legacy and/or slow devices) Figure 2.5: Early port-based system architecture

  12. 2.2 Main steps of the evolution (6) Pentium 4 Processor bus System Main Memory PCI E.x16 (SDRAM/) controller Hub interface 1xIDE/ PCI E.x1 (1x/2x) ATA 33/66/100 Peripheral LAN 10/100 controller 8x USB LPC (KBD, MS, FD, SP, PP, IR) AC'97 4x SATA HDAI PCI device adapter PCI bus Figure 2.6: Recent port-based system architecture

  13. 3. The evolution of Intel’s x86 processor bus

  14. 3. The evolution of Intel’s x86 processor bus Main features of the system-bus Pentium Pro PII, P4 PIII Width of the 8086 8088 80286 80386 80486 Pentium 1 1 20 24 32 address bus (bit) 20 32 2 32 36 36 2 3 1 32 1 64+8 data bus (bit) 16 8 32 64 64+8 16 4 4 Multiplexed 1 2 Bits 0,1 not implemented (Doubleword aligned) 3 Bits 0-2 not implemented (Quadword aligned) 4 For error protection Figure 3.1: Main features of the system-bus

  15. 4. Bus innovations introduced into Intel’s P4 chipsets

  16. 4. Bus innovations introduced into Intel’s P4 chipsets (1) 6/04 11/02 AGP 8x AGP 5/03 SATA 1.0a SATA 5/03 PCI 2.3 PCI 2/04 PCI-X 2.2 PCI-X 6/04 PCI Express PCI Express 1.0a 5/02 USB USB 2.0 12/01 AC' 97 AC' 97 2.3 HDAI HDAI 2001 2002 2003 2004 Figure 4.1: Bus innovations introduced into Intel’s P4 chipsets

  17. 4. Bus innovations introduced into Intel’s P4 chipsets (2) The principle of the AGP port Processor bus AGP Memory bridge Graphic chip Main memory (North bridge) I/O bridge Frame buffer (South bridge) AGP Main Features of the AGP port (Intel) Version 1.0 Version 2.0 (5/1998) (7/1998) (Based on Revision 2.1 (PCI) of the PCI) Clock speed 66 MHz Bus (Multiplexed 32-bit address bus Seperate 32-bit address bus /data bus) and 32-bit data bus (Transfer of 4-byte data blocks) Transfer of 8-byte data blocks 1x 2x 4x Transfer mode (AGP-66) (AGP-133) (AGP-266) (double (quadruple clocked) clocked) 264 MB/s 532 MB/s 1064 MB/s Transfer rate Figure 4.2.: Early evolution of the AGPport

  18. 4. Bus innovations introduced into Intel’s P4 chipsets (3) ISA EISA PCI PCI v.2 PCI v.2.11 PCI v.2.21, 3 PCI v.2.32 33 MHz 32-bit 8.33 MHz 8/16-bit 8.33 MHz 32-bit 33 MHz 64-bit 33/66 MHz 32/64-bit 33/66 MHz 32/64-bit 33/66 MHz 32/64-bit 1987 88 89 90 91 92 93 94 1995 96 97 98 99 2000 01 02 03 1: Both 3.3 V and 5 V is supported 2: Only 3.3 V is supported 3: Just improving the readibility of the standard text Figure 4.3: The evolution of the PCI bus standard

  19. 4. Bus innovations introduced into Intel’s P4 chipsets (3) PCI-X v.1.02 PCI-X v.2.02 66/133 MHz 64-bit 266/533 MHz 64-bit ISA EISA PCI PCI v.2 PCI v.2.11 PCI v.2.21, 3 PCI v.2.32 33 MHz 32-bit 8.33 MHz 8/16-bit 8.33 MHz 32-bit 33 MHz 64-bit 33/66 MHz 32/64-bit 33/66 MHz 32/64-bit 33/66 MHz 32/64-bit 1987 88 89 90 91 92 93 94 1995 96 97 98 99 2000 01 02 03 1: Both 3.3 V and 5 V is supported 2: Only 3.3 V is supported 3: Just improving the readibility of the standard text Figure 4.4: The introduction of the PCI-X

  20. 4. Bus innovations introduced into Intel’s P4 chipsets (5) Figure 4.5: Slot number limitations of the PCI-X bus Source: PCI Technology overview, Febr. 2003, http://www.digi.com/pdf/prd_msc_pcitech.pdf

  21. 4. Bus innovations introduced into Intel’s P4 chipsets (6) The PCI Express bus (3GIO) • PCI Express 1.0 introduced in 7/2002 • A link consists of 1x, 2x, 4x, 8x, 12x, 16x or 32x signal pairs (lanes) in each direction. • Transfer rate per lane per direction: 2.5 Gbits/s • Encoding 10 bits/byte Aggreagate bandwidth per lane (in both directions together): 2 x 2,5 /10 = 0,5 Gbyte/s

  22. 4. Bus innovations introduced into Intel’s P4 chipsets (7) ATA (PATA) cable ATA/PATA and SATA cables Figure 4.6.: Contrasting ATA/PATA and SATA cables

  23. 4. Bus innovations introduced into Intel’s P4 chipsets (8) 16-bit optionally High Quality audio 48 KHz sampling rate Modem extension 4 analog stereo inputs Multiple codec 2 analog mono inputs 4/6 channel output dedicated mic input May reside on any bus AC '97 Version 2.0 Revision 2.2 Revision 2.1 Version 1.0 (9/2000) (9/1997) (5/1998) 6/1996: 5 vendors (Intel, ADI, Creative Labs, National Semiconductor, Yamaha). Link: 5-wire digital (2 serial data lines) Audio Codec (up to 96 KHz sampling rate 18/20-bit AD/DA 120 dB dynamic range) resolution (Cost effective) capability (for multichannel audio solutions etc.) Digital controller (ISA, PCI, USB, 1394) or in an I/O-bridge Figure 4.7.: Early evolution of the AC ’97 bus

  24. 4. Bus innovations introduced into Intel’s P4 chipsets (9) High definition audio (HDA) AC’97 v.2.2 HDAI 6 8 No. of channels Resolution 20-bit 32-bit Sampling rate 96 kHz 192 kHz

  25. 4. Bus innovations introduced into Intel’s P4 chipsets (10) Figure 4.8: Peak bandwidth values and sustained data rates of peripheral buses

  26. 5. Chipsets of Intel’s P4 family

  27. 5. Chipsets of Intel’s P4 family 5.1 Overview of the P4 family 5.2 Desktop chipsets 5.3 Overview of DP server and workstation chipsets 5.4 DP server chipsets 5.5 DP workstation chipsets

  28. 5.1 Overview of the P4 family 3/02 11/02 2Q/05 ^ ^ ^ Xeon - MP line Foster-MP Gallatin Potomac m m m 0.18 /108 mtrs 0.13 /178 mtrs 0.09 1.4/1.5/1.6 GHz 1.5/1.9/2 GHz > 3.5 MHz On-die 256K L2 On-die 512K L2 On-die 1M L2 On-die 512K/1M L3 On-die 1M/2M L3 On-die 8M L3 (?) 400 MHz FSB 400 MHz FSB 5/01 2/02 6/04 11/02 2Q/05 ^ ^ ^ ^ ^ Xeon DP line Nocona Foster Prestonia-A Jayhawk Prestonia-B m m m m m 0.09 / 125 mtrs 0.18 /42 mtrs 0.13 /55 mtrs 0.09 0.13 /55 mtrs 2.8/3.0/3.2/3.4/3.6 GHz 1.4/1.5/1.7 GHz 1.8/2/2.2 GHz 3.8 GHz 2/2.4/2.6/2.8 GHz On-die 1M L2 On-die 256 K L2 On-die 512K L2 On-die 512K L2 On-die 1M L2 800 MHz FSB (Cancelled 5/04) 400 MHz FSB 400 MHz FSB 533 MHz FSB 1Q/05 ^ Irwindale-C m 0.09 3.0/3.2/3.4/3.6 GHz Desktop-line On-die 512K L2, 2M L3 5/03 3Q/05 11/00 2/04 11/02 1/02 5/02 ^ ^ ^ ^ ^ ^ ^ Northwood-C Tejas Willamette Northwood-A Northwood-B Northwood-B m m m m m m m m 0.18 /42 mtrs 0.13 /55 mtrs 0.09 /125mtrs 0.13 /55 mtrs 0.13 /55 mtrs 0.13 /55 mtrs 0.09 / 1.4/1.5 GHz 2.40C/2.60C/2.80C GHz 2.80E/3E/3.20E/3.40E GHz 2A/2.2 GHz 2.26/2.40B/2.53 GHz 3.06 GHz On-die 256K L2 On-die 512K L2 On-die 1M L2 On-die 512K L2 On-die 512K L2 On-die 512K L2 400 MHz FSB 800 MHz FSB 800 MHz FSB 400 MHz FSB 533 MHz FSB 533 MHz FSB 9/02 5/02 ^ ^ Celeron-line Willamette-128 Northwood-128 (Value PC-s) m m 0.18 0.13 1.7 GHz 2 GHz On-die 128K L2 On-die 128K L2 400 MHz FSB 400 MHz FSB 2001 2002 2003 2000 2005 2004 Cores with EM64T implemented but not enabled Cores supporting hyperthreading 3/04 ^ Gallatin m 0.13 /286 mtrs 2.2/2.7/3.0 GHz On-die 512K L2 On-die 2M/4M L3 400 MHz FSB m m PGA 603 PGA 603 m PGA 603 7/03 ^ Prestonia-C m 0.13 /178 mtrs 3.06 GHz On-die 512K L2, 1M L3 533 MHz FSB m m m m m PGA 603 PGA 603 PGA 604 PGA 603 PGA 603 11/03 11/04 ^ ^ 1 Extreme Edition 1 Irwindale-B Irwindale-A m 0.13 /178 mtrs m 0.13 /178mtrs 3.2EE GHz 3.4EE GHz On-die 512K L2, 2M L3 On-die 512K L2, 2 MB L3 1066 MHz FSB 800 MHz FSB m PGA 478 LGA 775 6/04 8/04 8/01 ^ ^ ^ 5 8,9,10 2,3 4 6,7 11 Prescott Prescott Willamette Prescott-F m m 0.18 /42 mtrs m 0.09 /125mtrs 0.09 /125mtrs 1.4 ... 2.0 GHz 4.0/4.2 GHz 2.8/3.0/3.2/3.4/3.6 GHz 3.20F/3.40F/3.60F GHz On-die 256K L2 On-die 1M L2 On-die 1M L2 On-die 1M L2 400 MHz FSB (Cancelled 5/04) 800 MHz FSB 800 MHz FSB m m m m m m m PGA 478 PGA 423 PGA 478 PGA 478 LGA 775 LGA 775 PGA 478 PGA 478 PGA 478 9/04 6/04 ^ ^ 12 13 Celeron-D Celeron-D m m 0.09 0.09 2.4/2.53/2.66/2.8 GHz 2.53/2.66/2.80/2.93 GHz On-die 256K L2 On-die 256K L2 533 MHz FSB 533 MHz FSB m m m LGA 775 PGA 478 PGA 478 PGA 478 Cores supporting EM64T Figure 5.1: Intel’s P4 cores (Netburst architecture)

  29. 5.2 Desktop chipsets (1) 8/04 Prescott F Northwood-B Willamette Willamette m m m m m m m PGA 423 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 Cores 11/00 11/02 1/02 2/04 Northwood-B Northwood-A Prescott 5/02 8/01 5/03 6/04 Northwood-C Prescott FSB 800 MHz 800 MHz 800 MHz 800 MHz 400 MHz 400 MHz 400 MHz 533 MHz 533 MHz HT HT HT HT HT HT EM64T EM64T Socket LGA 775 LGA 775 8/03 Chipsets 848P 10/02 9/03 5/03 5/03 865G/GV/PE 845GV/GE/PE 5/03 9/01 865P 845 5/02 845 G/E/GL 11/01 4/03 845 875P 6/04 9/03 6/04 915G/GV/P Figure 5.2: Intel’s chipsets designed for P4-based value and desktop PCs

  30. 5.2 Desktop chipsets (2) PCI Express x16 PCI Express x16 AGP 4X AGP 4X AGP 8X Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 AGP 8X ATA up to Graphics interface up to ICH6/ICH6R: ICH7/ICH7R: ICH2: ICH4: ICH5/ICH5R: ICH5/ICH5R: ICH 9/01 5/02 8/03 5/03 4/03 06/04 11/05 865xx/875P family 915xx family 975x 845 845xx family 848P (Grantsdale) (Brookdale) (Springdale/Canterwood) MCH/GMCH HT support HT HT no HT/HT HT HT no HT 800 MT/s 1066 MT/s 400 MT/s 533 MT/s 800 MT/s 800 MT/s FSB up to Dual channel Dual channel Single channel Single channel Single channel Dual channel Nr. of mem. channels DDR2 SDRAM DDR SDRAM DDR2 /DDR SDRAM SDR/DDR SDRAM SDR/DDR SDRAM DDR SDRAM Memory (unbuffered) (unbuffered) (unbuffered) (unbuffered) (unbuffered) (unbuffered) 2 GB 2 GB 2 GB 4 GB 4 GB 8 GB Max. memory DDR 400/DDR2 533 DDR2 667 DDR 266 DDR 333 DDR 400 DDR 400 DRAM speed up to Additional high speed CSA CSA 1 interface SATA 1.0a SATA 1.0a SATA 1.0a SATA 1.0a SATA 10/100 Mbit/s 10/100 Mbit/s LAN 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s PCI 2.3 PCI 2.3 PCI 2.2 PCI 2.2 PCI 2.3 PCI 2.3 PCI 2 2 PCI Express x1 PCI Express x1 1.0a PCI Express x1 1.0a USB 2.0 USB 2.0 USB 1.1 USB 2.0 USB 2.0 USB 2.0 USB AC' 97 2.3 3 AC' 97 2.3 AC' 97 2.3 AC' 97 2.1 AC' 97 2.3 AC' 97 2.3 AC' 97 HDAI HDAI 3 HDAI 1 The Communications Streaming Architecture (CSA) interface of the MCH provides a link to a Gigabit Ethernet Controller (GbE), e.g. to Intel's 82547EI GbE controller 2 A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds. (e.g. Intel's 82571EB dual channel GbE controller) 3 The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently Figure 5.3: The evolution of Intel’s chipset families designed for P4-based value/mainstream desktops

  31. 5.2 Desktop chipsets (4) BIOS P4 FSB 4 Max. 2/4 GB SDRAM SDRAM MCH 1 PC 133, DDR 200/266/333/400, DDR2 400/533 VGA interface unbuffered, ECC opt. 3 (845/845xx/848P/865xx/ 2 SDRAM 3 AGP 4X/8X/PCI Express x.16 SDRAM 875P/915xx) interface HI 1.5/DMI 5 6 ICH4 ICH6(R) ICH2 ICH5(R) 5 6 ICH2 ICH4 ICH5(R) ICH6(R) 6x v2.3 7x v2.3 6x v2.2 6x v2.2 PCI 2 2 2 1 ATA/100 PCI-X 5 6 4 2 SATA ICH 4 PCI Express x1 LAN 10/100 8x v2.0 USB 8x v2.0 4x v1.1 6x v2.0 GPI0 v2.3 AC/97 v2.1 v2.3 v2.3 LPC HDAI 5 6 ICH2/4/5/5R /6/6R 915xx 845xx 848P 845 845xx 848P 915xx 845 FWH 865xx 865xx 875P 875P 1 The chipsets including the letter G in their designation provide an integrated graphics controller. 2 The chipsets including the letters GL or GV in their designation don't have an AGP or PCI Express x16 interface. 3 The 865xx, 865 and 915xx chipsets have a dual channel memory link.. 4 The 845 has a max. memory of 3 GB for SDR SDRAMs. 5 The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation. 6 The ICH6R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation. Figure 5.4: The evolution of chipsets intended primarily for P4-based value/mainstream desktops

  32. 5.2 Desktop chipsets (3) Figure 5.5: Main features of Intel’s I/O Control Hubs (ICH) used in P4-based chipsets

  33. 5.2 Desktop chipsets (1) 8/04 Prescott F Northwood-B Willamette Willamette m m m m m m m PGA 423 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 Cores 11/00 11/02 1/02 2/04 Northwood-B Northwood-A Prescott 5/02 8/01 5/03 6/04 Northwood-C Prescott FSB 800 MHz 800 MHz 800 MHz 800 MHz 400 MHz 400 MHz 400 MHz 533 MHz 533 MHz HT HT HT HT HT HT EM64T EM64T Socket LGA 775 LGA 775 8/03 Chipsets 848P 10/02 9/03 5/03 5/03 845GV/GE/PE 865G/GV/PE 9/01 845 5/03 865P 5/02 11/01 845 845 G/E/GL 4/03 875P 6/04 9/03 6/04 915G/GV/P Figure 5.6: Intel’s chipsets designed for P4-based value and desktop PCs

  34. 5.2 Desktop chipsets (5) m m PGA 478 PGA 478 m m PGA 478 PGA 478 Features 845xx family MCH/GMCH (Brookdale) Memory Single channel SDR/DDR SDRAM (unbuffered) 1 Max. memory 2 GB FSB 400 MHz 533/400 MHz 2 HT support HT not supported HT supported DRAM speed PC133, PC133, PC133, PC133 DDR 333/266 DDR 266/200 DDR 333/266 DDR 266/200 DDR 266/200 DDR 266/200 DDR 266/200 9/01 10/02 10/02 12/01 5/02 5/02 5/02 10/02 11/01 845 845 845PE 845G 845E 845GL 845GV 845GE Memory protection ECC (opt.) ECC (opt.) ECC (opt.) Integrated graphics (IG) IG IG IG IG Graphics interface up to AGP 4X AGP 4X AGP 4X AGP 4X AGP 4X AGP 8X ICH4: ICH ICH2: ICH2: ICH4: ICH4: ICH4: ICH4: ICH4: ATA up to Ultra ATA/100 PCI PCI 2.2 LAN 10/100 Mbit/s USB 2.0 USB 1.1 USB 1.1 USB 2.0 USB 2.0 USB 2.0 USB 2.0 USB 2.0 USB AC '97 AC '97 2.1 AC '97 2.3 AC '97 2.3 AC '97 2.3 AC '97 2.3 AC '97 2.3 AC '97 2.3 AC '97 2.1 Target line at introduction P4 P4 Celeron/P4 P4 P4 Celeron/P4 P4 P4 Northwood-Bwith HT Northwood-128/Northwood-B with HT Target core at introduction Northwood-A Willamette-128/ Northwood-A Northwood-B with HT Willamette 0.18m 0.13m 0.18m 0.13m 1 The 845 has a max. memory of 2 GB for DDR SDRAMs and 3 GB for SDR SDRAMs. 2 At introduction of the 845G and 845E chipsets (5/02) Intel did not made any notice about supporting hyperthreading. But in 10/02 Intel revealed that the enhanced 845G (B stepping) and the original 845E do support hyperthreading with upgraded BIOSs. Figure 5.7: Main features of Intel’s 845xx family of chipsets

  35. 5.2 Desktop chipsets (6) Ultra ATA/100 (2 ports) P4 Northwood FSB 400/533 MHz 1 VGA Max. 2 GB 1,2 845xx SDRAM DDR 200/266/333 SDRAM interface unbuffered, no ECC (G)MCH 3 AGP 4x HI 1.5 LAN 10/100 MbE c. MbE PCI v.2.2 GbE c. GbE ICH4 PCI v.2.2 (3-6 slots) GPIO USB 2.0 (4-6 ports) AC'97 v.2.3 Audio CODEC LPC FWH SIO FD KB MS SP PP 1 The chipsets including the letter G in their designation provide an integrated VGA controller. 2 Mainboards based on the 845 chipset have a different configuration since they work with the ICH2. 3 The chipsets 845GL/GV don't offer an AGP interface. Figure 5.8: Typical configuration of a value/desktop motherboard based on Intel’s 845xx family of chipsets

  36. 5.2 Desktop chipsets (1) 8/04 Prescott F Northwood-B Willamette Willamette m m m m m m m PGA 423 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 PGA 478 Cores 11/00 11/02 1/02 2/04 Northwood-B Northwood-A Prescott 5/02 8/01 5/03 6/04 Northwood-C Prescott FSB 800 MHz 800 MHz 800 MHz 800 MHz 400 MHz 400 MHz 400 MHz 533 MHz 533 MHz HT HT HT HT HT HT EM64T EM64T Socket LGA 775 LGA 775 8/03 Chipsets 848P 10/02 9/03 5/03 5/03 865G/GV/PE 845GV/GE/PE 5/03 9/01 865P 845 5/02 845 G/E/GL 11/01 4/03 845 875P 6/04 9/03 6/04 915G/GV/P Figure 5.9: Intel’s chipsets designed for P4-based value and desktop PCs

  37. 5.2 Desktop chipsets (7) Features 915xxfamily (Grantsdale) MCH/GMCH HT supported HT support Memory Dual channel DDR2/DDR SDRAM (unbuffered, no ECC) Max. memory 4 GB 1 FSB 533 MHz 800/533 MHz DDR 400/333 DRAM speed DDR2 533/400, DDR 400/333 9/04 6/04 9/04 6/04 4 910GL 915G 915GV 915P (Grantsdale-GL) (Grantsdale-V) (Grantsdale-G) (Grantsdale-P) IG Integrated graphics (IG) IG IG Graphics interface up to PCI Express x16 PCI Express x16 ICH ICH6: IDE up to Ultra ATA/100 SATA SATA 1.0a PCI Express PCI Express x1 1.0a 2 PCI PCI 2.3 LAN 10/100 Mbit/s 3 AC '97 AC '97 2.3 3 HDAI HDAI supported Target line at introduction Celeron /P4 Celeron Celeron D/Prescott without EM64T Target core at introduction Celeron D 0.09 m 0.09 m m PGA 478/LGA 775 LGA 775 1 The max. memory of the 910GL is restricted only to 2 GB. 2 A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds (e.g. Intel's 82571EB dual channel GbE controller). The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently. 3 Supports processors also in socket PGA 478. 4 m Figures 5.10: Main features of Intel’s 915xx family of chipsets

  38. 5.2 Desktop chipsets (8) P4 Prescott FSB 533/800 MHz PCI E. x16 SDRAM 1 SDRAM VGA Max. 4 GB 915xx 1 interface DDR 333/400, DDR2 400/533 unbuffered, no ECC (G)MCH SDRAM 2 PCI E. x16 SDRAM interface DMI LAN 10/100 MbE c. MbE PCI v.2.3 Ultra ATA/100 PCI v.2.3 (1 port) (2-4 slots) PCI E. x1 GbE c. GbE SATA ICH6 (4 ports) PCI E. x1 (1-2 ports) GPIO USB 2.0 (8 ports) AC'97 v.2.3 Audio CODEC LPC FWH SIO FD KB MS SP PP 1 The chipsets including the letter G in their designation provide an integrated VGA controller. 2 The 915GL/GV chipsets don't offer a PCI Express x16 interface. Figure 5.11: Typical configuration of a value/desktop motherboard based on Intel’s 915xx family of chipsets

  39. 5.3 Overview of DP server and workstation chipsets m m m m PGA 603 PGA 603 PGA 603 PGA 603 5/01 2/02 11/02 7/03 6/04 Cores Foster Prestonia-A Prestonia-C Prestonia-B Nocona 400 MHz 400 MHz 533 MHz 533 MHz FSB 800 MHz HT HT HT HT HT EM64T EM64T Socket m PGA 604 Chipsets 8/04 E7320 DP-servers 11/02 2/02 E7501 E7500 8/04 E7520 DP-workstations 5/01 860 6/04 E7525 11/02 E7505 Figure 5.12: Intel’s chipsets designed for P4-based DP-servers and workstations

  40. 5.4 DP server chipsets (1) 5/01 E75xx/E73xx family Features 860 MCH HT support HT supported Nr. of mem. channels Dual channel SDRAM Dual channel Memory (registered, ECC) RDRAM 1 Max. memory 4 GB 16 GB Memory protection ECC (opt.) 400 MHz 400 MHz 800 MHz FSB 533 MHz EM64T supported EM64T support PC 800/600 DDR 266 /200 DDR 333 DRAM speed DDR 200 DDR 333/266 DDR2 400 DDR2 400 11/02 6/04 8/04 2/02 11/02 8/04 1 E7525 2 E7501 E7520 E7500 E7505 E7320 (Tumwater) (Plumas) (Placer) (Lindenhurst-VS) (Lindenhurst) Aim DP WS DP WS DP server DP server DP WS DP server DP server PCI Express x16 Graphics interface up to AGP 8X AGP 4X Additional high speed if. 1x PCI Express x8 3x PCI Express x8 3x HI 2.0 1x HI 2.0 2x HI 3x HI 2.0 1x PCI Express x8 4 4 4 4 4 RAS/RASUM RASUM RASUM 4 RASUM RASUM RAS RASUM 4 3 3 3 ICH5R:/6300ESB: ICH5R:/6300ESB: ICH ICH3-S: ICH3-S: ICH4: ICH5R:/6300ESB: ICH2: 4 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 Ultra ATA/100 IDE up to SATA 1.0a SATA SATA 1.0a SATA 1.0a PCI 2.3/PCI 2.2 PCI PCI 2.3/PCI 2.2 PCI 2.3/PCI 2.2 PCI 2.2 PCI 2.2 PCI 2.2 PCI 2.2 /PCI-X 2.2 PCI-X /PCI-X 2.2 /PCI-X 2.2 PCI Express x1 USB 2.0 USB 1.1 USB USB 1.1 USB 1.1 USB 2.0 USB 2.0 USB 2.0 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s 10/100 Mbit/s LAN AC '97 2.2 AC '97 2.2/AC '97 2.3 AC '97 2.1 AC' 97 AC '97 2.2 AC '97 2.3 AC '97 2.2/AC '97 2.3 AC '97 2.2/AC '97 2.3 Target cores at introduction Foster Prestonia-A Nocona Prestonia-B 0.18m/m PGA 603 0.13m/m 0.09m/m Technology/Socket PGA 603 PGA 604 1 The 7505 supports also unbuffered DDR SDRAMs. 2 The 7520 includes an integrated four channel DMA engine in contrast to the E7320. 3 The ICH5R incorporates a RAID controller (Redundant Arrays of Indepentdent Disks) that utilizes the dual SATA ports for a high-performance RAID Level 0 configuration. 4 Reliability, Availability, Serviceability, Usability, Manageability Figure 5.13: The evolution of Intel’s chipsets designed for P4 Xeon-based dual processor (DP) servers and workstations (WS)

  41. 5.4 DP server chipsets (2) P4 P4 Xeon Xeon FSB HI 2.0/PCI E. x8 SDRAM 1 Max. 8-32 GB MCH SDRAM interface DDR 200/266/333/400, DDR2 400 HI 2.0/PCI E. x8 High speed if. 2 with RASUM registered, ECC SDRAM SDRAM HI 2.0/PCI E. x8 interface 3 (E7500/7501/7320 /7520) HI 1.5 5 6 ICH3-S ICH5R 6300ESB 5 6 ICH3-S ICH5R 6300ESB 6x v2.2 6x v2.3 4x v2.2 PCI 2 2 2 ATA/100 PCI-X 4x v.2.2 SATA 5 6 2 2 ICH PCI Express x1 LAN 10/100 USB 8x v2.0 6x v1.1 4x v2.0 GPI0 5 (ICH3-S/5R /6300ESB) AC' 97 v2.2 v2.3 v2.2 LPC HDAI E7500 E7520 E3520 E7500 E7520 E7320 FWH E7501 E7501 BIOS The 16-bit HI 2.0 link is used to add PCI/PCI-X bridges (6700PXH), while the PCI Express x8 links are usually configured as two independent x4 ports, 1 each providing the possibility to add a PCI/PCI-X brigde (e.g. 6700PXH) or a dual GbE controller Reliability, Availability, Serviceability, Usability, Manageability 2 The E7320 has only a single PCI Express x8 high speed interface 3 An external SATA controller is needed only in connection with the ICH3-S 4 The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation 5 The 6300ESB SATA supports soft RAID. 6 Figure 5.14: The evolution of DP-server chipsets of P4 cores

  42. 5.4 DP server chipsets (3) P4 P4 Prestonia Prestonia FSB 400/533 MHz PCI-X v.2.2 (1-2 slots) HI 2.0 SDRAM E7500/E7501 GbE SDRAM GbE c. 8/12/16 GB interface HI 2.0 PCI-X MCH DDR 200/266 bridge registered, ECC opt. SATA c. SATA SDRAM SDRAM (with RASUM) HI 2.0 interface SCSI c. SCSI HI 1.5 PCI-X v.2.2 (1-2 slots) SVGA Video c. PCI v.2.2 Ultra ATA/100 MbE MbE c. (2 ports) ICH3-S PCI v.2.2 (3 slots) GPIO USB v. 1.1 (5 ports) LPC FWH SIO FD KB MS SP PP Figure 5.15: Typical configuration of a DP-server motherboard based on Intel’s E7500/E7501 chipsets

  43. 5.4 DP server chipsets (4) P4 P4 Nocona Nocona FSB 800 MHz PCI-X v.1.0b (1 slot) PCI E. x8 SDRAM E7520 SDRAM GbE GbE c. 16/24/32 GB interface PCI-X PCI E. x8 MCH DDR 266/333, DDR2 400 bridge SCSI c. SCSI registered, ECC opt. SDRAM SDRAM PCI E. x8 (with RASUM) PCI E. x8 interface PCI-X v.1.0b (or 2x x4) (1-2 slot) HI 1.5 PCI v.2.3 Video c. SVGA Ultra ATA/100 (2 ports) PCI v.2.3 (0-1 slot) SATA ICH5R (2 ports) USB v. 2.0 (4 ports) GPIO AC' 97 v.2.3 LPC FWH SIO FD KB MS SP PP Figure 5.16: Typical configuration of a DP-server motherboard based on Intel’s E7520 chipset (including the ICH5R)

  44. 5.5 DP workstation chipsets (1) P4 P4 Xeon Xeon FSB Max. 16 GB SDRAM 1 MCH SDRAM AGP 4X/8X/PCI E. x16 interface DDR 200/266/333, DDR2 400 2 with RASUM registered, ECC opt. SCSISATAGbE SDRAM SDRAM HI 2.0, PCI E x8 PCI-X interface 2,3 bridge (860 /E7505/7525) HI 1.5 4 5 ICH2 6300ESB 4 ICH4 ICH5R 5 ICH5R 6300ESB ICH2 ICH4 6x v2.2 4x v2.2 6x v2.2 6x v2.3 PCI 2 2 2 2 ATA 4x v.2.2 PCI-X 4 5 2 2 SATA ICH PCI Express x1 LAN 10/100 USB 4x v1.1 8x v2.0 4x v2.0 6x v2.0 GPI0 (ICH2/4/5R/6300ESB) v2.1 AC' 97 v2.3 v2.3 v2.2 LPC HDAI 860 E7505 E7525 E7525 860 E7505 E7525 E7525 FWH BIOS 1 Reliability, Availability, Serviceability, Usability, Manageability 2 The first chipsets of this line (the 860) worked with DRDRAMs while using PC 600/800. 3 The MCH of the 860 provides two 16-bit high speed interfaces, to add PCI v2.2 bridges (P64H). 4 The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation 5 The 6300ESB SATA supports soft RAID. Figure 5.17: The evolution of DP-workstation chipsets of P4 cores

  45. 5.5 DP workstation chipsets (2) P4 P4 Prestonia B/C Prestonia B/C PCI-X v.2.2 (1-2 slots) FSB 533 MHz GbE GbE c. HI 2.0 PCI-X SDRAM E7505 SDRAM bridge 8/12 GB interface SATA SATA c. DDR 200/266 MCH AGP 8x registered, ECC opt. SDRAM SCSI c. SCSI SDRAM (with RASUM) interface PCI-X v.2.2 (1-2 slots) HI 1.5 PCI v.2.2 MbE c. MbE Ultra ATA/100 (2 ports) PCI v.2.2 (1-2 slots) ICH4 USB 2.0 (4 ports) GPIO AC'97 v.2.2 Audio CODEC LPC FWH SIO FD KB MS SP PP Figure 5.18: Typical configuration of a DP-workstation motherboard based on Intel’s E7505 chipset

  46. 5.5 DP workstation chipsets (3) P4 P4 Nocona Nocona FSB 800 MHz SDRAM PCI E. x16 E7525 SDRAM 16/24/32 GB interface MCH DDR 266/330 x4 PCI E. x8 registered, ECC opt. SDRAM SDRAM (with RASUM) x4 PCI-X PCI-X interface GbE c. GbE c. bridge HI 1.5 PCI-X v.2.2 GbE c. GbE PCI v.2.2 Ultra ATA/100 ICH (1-2 slots) (2 ports) PCI-X v.2.2 SATA (2 slots) (2 ports) 6300ESB USB 2.0 GPIO (4 ports) AC'97 v.2.2 Audio CODEC LPC SIO FWH FD KB MS SP PP Figure 5.19: Typical configuration of a DP-workstation motherboard based on Intel’s E7525 chipset

  47. 6. Bandwidth considerations

  48. 6. Bandwidth considerations (1) 8 * f Mbyte/s FSB 8 * f Mbyte/s SDRAM Width Peak aggregate bandwidth FSB 64-bit SDRAM-interface 64-bit Figure 6.1: Main features of the FSB and SDRAM interfaces

  49. 6. Bandwidth considerations (2) Figure 6.2: Main features of MCH/ICH interfaces used in Intel’s P4-based chipsets

  50. 6. Bandwidth considerations (3) Figure 6.3: Main features of high speed MCH interfaces of Intel’s P4-based chipsets

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