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Dezső Sima September 2008

5. Synchronous memory modules. Dezső Sima September 2008. (Ver. 1.0).  Sima Dezső, 2008. Overview. 1. Design space of memory modules. 2. Basic features. 3. Registering. 4. ECC. 5. Presence detect. 6. Keying. 7. Summing up the main features of memory modules.

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Dezső Sima September 2008

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  1. 5. Synchronous memory modules Dezső Sima September 2008 (Ver. 1.0)  SimaDezső, 2008

  2. Overview 1. Design space of memory modules 2. Basic features 3. Registering 4. ECC 5. Presence detect 6. Keying 7. Summing up the main features of memory modules 8.References

  3. 1. Design space of memory modules (1) Layout of memory modules Layout of memory modules Basic features of memory modules Keying Registering (Buffering) ECC Presence detect Figure: Main dimensions of the design space of the layout of memory modules

  4. 2. Basic features (1) Basic features of memory modules No. of module sides populated No. of ranks provided on the module Module width (Data/Data+ECC) Module type Figure: Basic features of memory modules

  5. 2. Basic features (2) Memory card (build up of DIPs) Module types Figure : Main module types of general use

  6. 2. Basic features (3) Memory cards • DRAMs packaged in DIPs1 mounted on a PC-card 2 • attached via the ISA bus or a dedicated bus of the motherherboard • used as the main memory or add-on memory in early PCs (8088 or 80286 based). 1 DIP: Dual In-line Package 2 PC: Printed Circuit

  7. 2. Basic features (4) Figure: 8-Bit ISA PC Memory Card (Gold 5150) [12]

  8. 2. Basic features (5) SIPP (Single In-linePin Package) Module types Memory card (build up of DIPs) Figure : Main module types of general use

  9. 2. Basic features (6) 1 Byte wide 30 pins Figure: SIPP module [11]

  10. 2. Basic features (7) SIMM (Single In-lineMemory Module) Module types Memory card SIPP (Single In-linePin Package) (build up of DIPs) Figure : Main module types of general use

  11. 2. Basic features (8) 1-Byte/30-pin FPM FPM/EDO 4-Byte/72-pin Figure: SIMM modules

  12. 2. Basic features (9) SIMM 72-pin 30-pin (32/36-bit) Width (Data/Data+parity) (8/9-bit) DRAM-type FPM FPM EDO First introducedin Intel’s chipsets (~1986?) 1993 1995 Voltage 5 V 5 V/3.3 V 5 V/3.3 V 4 – 64 MB 2 – 32 MB Typ. module capacity 256 KB – 8 MB 486 Pentium late 386 486 early Pentium Typ. use in connectionwith the processors 286 early 386 Figure : Main features of SIMM modules

  13. 2. Basic features (10) Module types Memory card SIMM DIMM SIPP (Single In-linePin Package) (Single In-lineMemory Module) (Dual In-lineMemory Module) (built up of DIPs) Figure : Main module types of general use

  14. SDRAM 168-pin DDR 184-pin DDR2 240- pin DDR3 240-pin Figure: DIMM modules (8-Byte wide)

  15. 2. Basic features (12) DIMM 240-pin 168-pin 184-pin (64/72-bit) Width (Data/Data+ECC) (64/72-bit) (64/72-bit) DRAM-type FPM EDO SDRAM DDR DDR2 DDR3 DIMM first intro.in Intel’s chipsets (1995) (1996) (1996) (2002) (2004) (2007) Voltage 5 V/3.3V 5 V/3.3 V 3.3 V 2.5 V 1.8 V 1.5 V 512–496 256–4096 Typ. capacity [MB] 1-16 1-16 16-512 128 –1024 Core2 Duo Pentium 4 Pentium D Core2 Duo Typ. use withthe processors Pentium (3.3V) Pentium (3.3V) Pentium (3.3V) Pentium II Pentium III Pentium 4 Figure : Main features of DIMMs

  16. 2. Basic features (13) SODIMM (Small OutlineDual In-lineMemory Module) Module types Memory card SIMM DIMM SIPP (Single In-linePin Package) (Single In-lineMemory Module) (Dual In-lineMemory Module) (build up of DIPs) Figure : Main module types of general use

  17. 2. Basic features (14) SDRAM 4 Byte/72 pin DDR2 8 Byte/200 pin Figure: SO-DIMM modules

  18. 2. Basic features (15) SODIMM 200-pin 72-pin 144-pin 204-pin 32-bit 64-bit 64-bit 64-bit Width (Data) SDRAM FPM EDO EDO DDR DDR2 DDR3 1996 Est. year of intro. ~1994 ~1995 ~1996 2002 2004 2007 64-512 Typ. capacity [MB] 4-64 4-64 8-64 128 –1024 256–2048 512–4096 3.3 V Voltage 5 V/3.3V 5 V/3.3 V 3.3 V 2.5 V 1.8 V 1.5 V Figure : Main features of SODIMM modules

  19. 2. Basic features (16) Modules width (Data/Data+ECC) 1-byte wide modules 4-byte wide modules 8-byte wide modules (64/72-bits) (8/9-bits) (32/36-bits) Pentium (1993), and subsequent processors: 8-byte wide data bus 8088-based PCs (1981): 1-byte wide data bus, 80286 based PCs (1984): 2-byte wide data bus 386 (1985) and 486 (1988) based PCs: 4-byte wide data bus Figure : Memory module widths vs data bus width of the processor bus in x86 processors

  20. 2. Basic features (17) Number of memory module sides populated Memory module populated on both sides Memory module populated on one side • Includes usually two ranks • but may include also • just one rank • Includes usually one rank Figure: Population alternatives of memory modules

  21. 2. Basic features (18) Number of ranks provided on the memory module Two ranks Single rank Both alternatives are used by the manufacturers Figure: Number of ranks provided on the memory module

  22. 3. Registering (1) Registering Registering Registered modules Unregistered modules Main memories of desktops/laptops Main memories of servers Typical use DIMM With module type -- ECC Typically yes Typically no Figure: Registering alternatives of memory modules

  23. 3. Registering (2) Unregistered DIMMs (UDIMMs) Typical use: in desktops/laptops (Memory capacities: up to a few GB) Registered DIMM (RDIMM) Typical use: in servers (Memory capacities: a few tens of GB) Problems arising while implementing higher memory capacities Higher memory capacities need more modules Higher loading the lines Signal integrity problems Buffering address and command lines, Phase locked clocking of the modules

  24. 3. Registering (3) ECC Register Register PLL Typical implementation • Two register chips, for buffering the address- and command lines • A PLL (Phase locked loop) unit for deskewing clock distribution. Figure:Typical layout of a registered memory module with ECC [24]

  25. 3. Registering (4) S D R A M S D R A M S D R A M S D R A M S D R A M S D R A M S D R A M S D R A M S D R A M Data From / To Motherboard PI6CV857PLL PI74SSTV168 57 Register PI74SSTV168 57 Register Input ClockforMotherboard Address ControlfromMotherboard Address/ControlformMotherboard Figure: Example. Block diagram of a registered DDR DIMM [29]

  26. 3. Registering (5) Register chips Aim Buffering address and control lines, • in order to increase the number of supported DIMM slots (max. mem. capacity) • needed first of all in servers, • by reducing signal loading in a memory channel. Number of register chips required • Synchronous memory modules have about 20 - 30 address and control lines, • Register chips buffer usually 14 lines, Typically, two register chips are needed per memory module [29].

  27. 3. Registering (6) DQM CS# U12 DQ DQ DQ DQ DQ DQ DQ DQ DQM DQM DQM DQM DQM DQM DQM DQM CS# CS# CS# CS# CS# CS# CS# CS# U11 U3 U1 U10 U2 U14 U4 U13 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ R E G I S T E R PPL Functional block diagram of a registered SDRAM DIMM [28], with one rank, built up of • 8 x8 SDRAMs • 1 ECC unit • 1 Register unit • 1 PLL unit and • 1 SPD unit.

  28. 3. Registering (7) R E G I S T E R REGE: Register enable signal Registering (buffering) the address and control lines Figure: Registered signals in case of an SDRAM memory module [28] Note: Data (DQ) and data strobe (DQS) signals are not registered.

  29. 3. Registering (8) PLL unit (Phase locked loop unit) The need to deskew the clock signal distributed on the memory module • Clock signals (CK) are sent in parallel with the address and control signals from • the memory controller and need to be distributed to the DRAM devices and register units • mounted on the module. • Clock distribution means amplification and branching the clock signal typically up to • 9-18 DRAM devices and 2 register units (one/two sided populated modules). • The circuitry implementing clock distribution causes a skew between the input clock • and the clock signals arriving at the DRAM and register chips. • Clock skew reduces the width of the usable window and thus limits the operation speed. • A PLL mounted to the memory module deskews the clock and thus improves timing • budget and raises operating speed.

  30. 3. Registering (9) Figure: The task of clock distribution in case of a double sided registered memory module (actually in case of an SDRAM module) (based on [21])

  31. 3. Registering (10) CK-1 CK-2 Skew Figure: Skew due to capacitive loading of the clock line (CK-2)

  32. 3. Registering (11) Center aligned clock Skewed clock Available DVW Available DVW Data Data CK CK tS tS tH tH Min. DVW Min. DVW Figure: Reduction of operation tolerances due to clock skew (ideal signals assumed) A larger skew would even jeopardize or prevent correct operation Deskewing of clock distribution is needed

  33. 3. Registering (12) Principle of deskewing by means of a PLL (Phase Locked Loop) unit The signal to be deskewed VCO: Voltage Controlled Oscillator Operation The PLL unit compares the phases of the Ref. signal and the signal to be deskewed, generates an error signal and controls the VCO with this error signal. Figure: Principle of deskewing by means of a PLL (Based on [20])

  34. 3. Registering (13) PLL PLL PLL Figure: Typical clock distribution schemes of one- and two-sided SDRAM modules [28], [41], [21] Note: CK0 is an open ended signal

  35. 3. Registering (14) PLL PLL Figure: Typical clock distribution schemes of two-sided DDR/DDR2 modules [13], [14] Note: CK0 is a differential signal

  36. 3. Registering (15) Note • In case of SDRAM devices the clock signal is used to gate in the address, control and data lines, • in case of DDR/DDR2/DDR3 devices the clock signal is used to gate in the address and control lines, whereas the data lines are gated in by the data strobe signals (DQS). Examples PLL on an SDRAM modules

  37. 3. Registering (16) DQM CS# U12 DQ DQ DQ DQ DQ DQ DQ DQ DQM DQM DQM DQM DQM DQM DQM CS# CS# CS# CS# CS# CS# CS# U2 U10 U3 U11 U1 U14 U13 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQM CS# U4 DQ DQ DQ DQ DQ DQ DQ DQ R E G I S T E R PPL SPD EEPROM WP A0 A1 A2 Functional block diagram of a registered SDRAM DIMM with one rank [28], built up of • 8 x8 SDRAMs • 1 ECC unit • 1 Register unit and • 1 PLL unit.

  38. 3. Registering (17) CMU NW CS# DQS DQS# CMU NW CS# DQS DQS# U21 U15 TRDQS TRDQS TRDQS# TRDQS# DQ DQ CMU CMU CMU CMU CMU CMU CMU CMU CMU NW NW NW NW NW NW NW NW NW CS# CS# CS# CS# CS# CS# CS# CS# CS# DQS DQS DQS DQS DQS DQS DQS DQS DQS DQS# DQS# DQS# DQS# DQS# DQS# DQS# DQS# DQS# DQ DQ U2 U4 U9 U5 U8 U11 U10 U1 U3 TRDQS TRDQS TRDQS TRDQS TRDQS TRDQS TRDQS TRDQS TRDQS TRDQS# TRDQS# TRDQS# TRDQS# TRDQS# TRDQS# TRDQS# TRDQS# TRDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ ZQ CMU NW CS# DQS DQS# CMU NW CS# DQS DQS# U20 U14 TRDQS TRDQS TRDQS# TRDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ CMU NW CS# DQS DQS# CMU NW CS# DQS DQS# U19 U13 TRDQS TRDQS TRDQS# TRDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ CMU NW CS# DQS DQS# CMU NW CS# DQS DQS# U18 U12 TRDQS TRDQS TRDQS# TRDQS# DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ CMU NW CS# DQS DQS# U17 TRDQS TRDQS# DQ Temperature senson/SPD EEPROM DQ DQ EVT A0 A1 A2 DQ DQ DQ DQ DQ R e g i s t e r a n d P L L DDR3SDRAM DDR3SDRAM Functional block diagram of a registered DDR3 DIMM with 2 ranks [15], built up of • 16 x8 DDR3 devices • 2 ECC unit • 1 Register and PLL unit and • 1 Temp. sensor/SPD unit.

  39. 3. Registering (18) R e g i s t e r a n d P L L Figure: Integrated register and PLL unit of a DDR3 DIMM [15]

  40. 3. Registering (19) SDRAMStack PLL OUT1 SDRAMStack IN Reg. 1 OUT ‘N’ Feedback Reg. 2 Implementation of the clock distrubution circuitry including a PLL unit Figure: Overview of a clock distribution circuitry intended for DDR devices [16]

  41. 3. Registering (20) The clock distribution circuitry including PLL became standardised by JEDEC in connection with DDR devices in 2000 [17] 10 outputs to the DDR devices and the register unit(s) Input of the feedback loop Phase lock between FBIN/FBOUT and CK Output of the feedback loop Figure: Block diagram of the clock distribution circuitry [17]

  42. 3. Registering (21) The operation of the PLL unit • The PLL unit compares the phases of the output clock signal (FBOUT) • and the input clock signal (CK) and generates an error signal which is fed back • to control the PLL unit in order to achieve a phase match between FBOUT/FBIN • and the incoming clock signal (CK) as close as possible. • The output of the PLL unit (Yi/Yi#) can be considered as the negatively delayed • clock signal (CK).

  43. 3. Registering (22) Use of PLLs in main memories In connection with the main memory PLLs are widely used to deskew signals or to align signal edges, such as • SDRAM/DDR/DDR2/DDR3 modules include PLLs to deskew clock distribution • on the memory card (as discussed above), • DDR/DDR2/DDR3 SDRAM devices include PLLs to achieve a phase match of the • Data Strobe Signal (DSQ) with the data signals (DQ) in case of data reads, • DDR/DDR2/DDR3 SDRAM memory controllers use PLLs • in case of data writes to center align write data (DQ) with the data strobe signal (DQS) and align the edges of DQS with CK, • in case of data reads the device sends edge aligned data (DQ) with the DQS, it is the task of the controller’s PLL to shift DQS edge to the center of the data read. • In multi module memory systems PLLs are utilized to deskew clocking.

  44. 3. Registering (23) Figure: Aligning read and write data in DDR/DDR2/DDR3 devices [19]

  45. 3. Registering (24) MemoryControlleror BusRe-driveChip 1 2 3 4 PLLorClockBuffer Remark If there are multiple DRAM modules connected to a memory channel an extra PLL is needed to deskew the multi-module memory system Figure: Deskewing a multi-module memory system by a PLL [29]

  46. 4. ECC (1) ECC Module with ECC Figure:Registered memory card with ECC [24]

  47. 4. ECC (2) ECC basics (as used in SDRAMs) Implemented as SEC-DED(Single Error Corretion Double Error Detection) Single Error Correction For D data bits P check-bits are taken. Figure: The code word The minimum number of check-bits (P) for single bit error corection ? Requirement: 2P ≥ the minimum number of states to be distinguished.

  48. 4. ECC (3) The minimum number of states to be distinguished: • D + P states • to specify the bit position of a possible single bit error in the code word • for both data and check bits, • one additional state to specify the „no error” state. the minimum number of states to be distinguished is: D + P + 1 Accordingly: to implement single bit error correction the minimum number of check bits (P) needs to satisfy the requirement: 2P ≥ D + P + 1

  49. 4. ECC (4) Double error detection an additional parity bit is needed to check for an additional error. Then the minimum number of check-bits (CB) needed for SEC-DED is: CB = P + 1 i.e. 2CB-1 ≥ D + CB -1 + 1 2CB-1 ≥ D + CB Table: The number of check-bits (CB) needed for D data bits

  50. 4. ECC (5) Principle of ECC coding A constructor matrix [C] defines the check-bits [CB]: [CB] = [D] × [C] E.g. The constructor matrix [C] used in [22] is:

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