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CEC 220 Digital Circuit Design VHDL in Sequential Logic

CEC 220 Digital Circuit Design VHDL in Sequential Logic. Lecture Outline. Sequential Logic in VHDL Design of Registers & Counters in VHDL. VHDL in Sequential Logic. Architecture Statements All architecture statements execute concurrently Process Statements – Sequential execution

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CEC 220 Digital Circuit Design VHDL in Sequential Logic

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  1. CEC 220 Digital Circuit DesignVHDL in Sequential Logic CEC 220 Digital Circuit Design

  2. Lecture Outline • Sequential Logic in VHDL • Design of Registers & Counters in VHDL CEC 220 Digital Circuit Design

  3. VHDL in Sequential Logic • Architecture Statements • All architecture statements execute concurrently • Process Statements – Sequential execution • The Process statement executes when any signal in the sensitivity list changes entity name architecture my_arc1 of my_box is signal sig1: bit; begin ?? <= ???; end my_arc1; process (CLK, …) begin ?? <= ???; end process; CEC 220 Digital Circuit Design

  4. VHDL in Sequential Logic • Conditional Assignment Statements • Outside of process blocks (concurrent statements) • Inside process blocks (sequential statements) F <= IN0 when A = “00” else IN1when A = “01” else IN2 when A = “10” else IN3; with A select F <= IN0 when A = “00”, IN1 when A = “01”, IN2 when A = “10”, IN3 when others; or case A is when “00” => F <= IN0; when “01” => F <= IN1; when “10” => F <= IN2; when others => F <= IN3; end case; if A = “00” then F <= IN0; elsifA = “01” then F <= IN1; elsifA = “10” then F <= IN2; else F <= IN3; end if; or CEC 220 Digital Circuit Design

  5. VHDL in Sequential Logic • Modeling a Gated S-R Latch process (G,S,R) begin if G=‘1’ then if S=‘1’ and R=‘0’ then Q<=‘1’; end if; if S=‘0’ and R=‘1’ then Q<=‘0’;end if; end if; end process; S Q G R Gate low Hold Set Reset - Why is the S=0 & R=0 case not included? - What will Q be when S=1 & R=1 (from the code above)? CEC 220 Digital Circuit Design

  6. VHDL in Sequential Logic • Modeling a Gated D Latch D Q G process (D, G) begin if G =‘1’ then Q <= D; end if; end process; Gate low Gate high Gate low - Why is the G = ‘0’ case not included? CEC 220 Digital Circuit Design

  7. VHDL in Sequential Logic • Modeling a JK Flip-Flop with Async. Set & Reset entity JKFF is port( J, K, SetN, RstN, CLK : in bit; -- inputs Q, QN: out bit); -- Q and QN are the outputs end JKFF; architectureJKFF_eqnsof JKFF is signalQint: bit; -- Internal value of Q begin Q <= Qint; QN <= notQint; - Why are J & K not in the sensitivity list ? process(SetN, RstN, CLK) -- AsyncronousSet and Reset begin ifRstN='0' thenQint <='0' after 5 ns; elsifSetN='0' thenQint <='1' after5 ns; elsifCLK'eventand CLK = '0' then-- falling edge of CLK Qint <= (J and not Qint) or (not K andQint) after 10 ns; end if; end process; endJKFF_eqns; - What will happen if RstN = ‘0’ & SetN= ‘0’ ? CEC 220 Digital Circuit Design

  8. VHDL in Sequential Logic • Modeling a JK Flip-Flop with Set & Reset • A simulation example Toggle SN Reset Hold Set Hold Toggle RN Toggle CEC 220 Digital Circuit Design

  9. VHDL in Sequential Logic • Modeling a 3-bit Rotating Register CLK CLK Initialization entityROTATER is port ( clk: inbit; Qout: outbit_vector(0 to 2) :="100"); end ROTATER; CLK CLK architectureROTATING_REG of ROTATER is entity DFF is port ( D, CLK : in bit; Q: outbit); end DFF; componentDFF port ( D, CLK: in bit; Q: outbit); end component; architectureDFF_eqnsof DFF is begin process(CLK) begin if CLK'eventand CLK = '0' then Q <= D; end if; end process; endDFF_eqns; signalQ0, Q1, Q2: bit; begin FF0: DFF port map(Q2, CLK, Q0); FF1: DFF port map(Q0, CLK, Q1); FF2: DFF port map(Q1, CLK, Q2); Qout <= Q0 & Q1 & Q2; end ROTATING_REG; CEC 220 Digital Circuit Design

  10. VHDL in Sequential Logic • Simulation results • Q0Q1 Q2 was initialized to be “100” 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 CEC 220 Digital Circuit Design

  11. VHDL in Sequential LogicUsing the IEEE Library • A 16-bit Up-Counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is port ( clk, rst: instd_logic; q: outstd_logic_vector(15 downto0)); end counter; + 16 Registers q 1 architecturemy_logicof counter is signalq_tmp: std_logic_vector(15 downto0); begin process(clk, rst) begin ifrst = '0' then q_tmp <= "0000000000000000"; elsifrising_edge(clk) then q_tmp <= q_tmp + 1; end if; end process; The “rising_edge” and “falling_edge” functions are defined in the IEEE Library rst clk The ‘+’ operator causes the generation of a 16-bit adder in hardware!! q <= q_tmp; endmy_logic; CEC 220 Digital Circuit Design

  12. VHDL in Sequential LogicUsing the IEEE Library • A 16-bit Up-Counter + 16 Registers q 1 rst clk CEC 220 Digital Circuit Design

  13. Next Lecture • Mealy and Moore State Machines CEC 220 Digital Circuit Design

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