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Direct Conversion Receivers. Qui Luu Dec 2, 2009. Agenda. Wireless communication architectures Dual IF Superheterodyne, Low IF Sampling Single IF Superheterodyne, High IF Sampling Direct (Zero-IF) Conversion Homodyne receiver challenges DC offset Quadrature errors Even order distortions

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direct conversion receivers

Direct Conversion Receivers

Qui Luu

Dec 2, 2009

agenda
Agenda
  • Wireless communication architectures
    • Dual IF Superheterodyne, Low IF Sampling
    • Single IF Superheterodyne, High IF Sampling
    • Direct (Zero-IF) Conversion
  • Homodyne receiver challenges
    • DC offset
    • Quadrature errors
    • Even order distortions
  • Origins of DC offset
    • LO feed through
    • Common mode mismatch
  • Theory behind quadrature errors
    • Amplitude and phase mismatch
  • Consequences of DC and Quadrature error
    • EVM
    • Occupy available bandwidth
  • Implementation of DC and quadrature correction
  • Results
  • Summary
receive architectures dual if superheterodyne low if sampling
Receive Architectures Dual IF Superheterodyne, Low IF Sampling

Cos(ωLO-ωIF)Cos(ωLO)=Cos(2ωLO-ωIF)+Cos(ωIF)

Cos(ωLO+ωIF)Cos(ωLO)=Cos(2ωLO+ωIF)+Cos(ωIF)

receive architectures dual if superheterodyne low if sampling4
Receive Architectures Dual IF Superheterodyne, Low IF Sampling
  • Large RF/IF content
  • RF front end
    • Fixed final LO frequency and mixer, reconfigurable first LO frequency and maybe mixer
    • Final IF amplifier HD2/HD3 may require sharper anti-alias filter
    • Distributed RF gain eases per block noise/gain/IP trade-off
  • Typically used for multi-band single carrier designs
  • IF ranges to 15MHz
slide5

Receive Architectures Single IF Superheterodyne, High IF Sampling

Cos(ωLO-ωIF)Cos(ωLO)=Cos(2ωLO-ωIF)+Cos(ωIF)

Cos(ωLO+ωIF)Cos(ωLO)=Cos(2ωLO+ωIF)+Cos(ωIF)

receive architectures single if superheterodyne high if sampling
Receive Architectures Single IF Superheterodyne, High IF Sampling
  • Cuts out one mixer stage
    • Puts the final mixer requirements on the ADC
    • Last IF mix done in digital domain (digital complex down mix)
  • RF front end
    • Band reconfigurable first LO frequency and maybe mixer
    • Final IF amplifier HD2 usually of no concern
    • Reduced RF gain distribution requires higher performing RF/IF
  • ADC needs good IF performance (nyquist or under-sample)
  • IF ranges from 100-300MHz
slide7

Receive ArchitecturesDirect (Zero-IF) Conversion

Phase and

Gain Error

LNA(t)=α1x(t)+α2x2(t)

input(t)=A1Cos(ω1t)+A2Cos(ω2t)

feedthrough(t)=α2A1A2Cos(ω2-ω1)t

Cos(ωRF) Cos(ωRF)=1+Sin2(ωRF)

Cos(ωSIG) Cos(ωSIG)=1+Sin2(ωSIG)

Phase and

Gain Error

homodyne receiver advantages and challenges
Homodyne Receiver Advantages and Challenges

Advantages:

  • Low component count leads to lower system cost
  • No image reject filter needed
  • Filtering requirements more relaxed at baseband
  • Gain stages at baseband provide power savings

Challenges:

  • DC offset appearing at baseband
      • Self mixing
      • Offset voltages
  • Images appearing symmetrically about zero frequency
      • I/Q mismatches in phase and amplitude
  • Even order nonlinearities
      • Two high frequency interferers close to the channel of interest can result in even order non-linearities that fall within the band of interest.
the imperfect i q demodulator
The Imperfect I/Q Demodulator

Gain

Imbalance

(G1,G2,G3,G4)

Imbalance

In Phase

Splitter

Offset

Voltages

imperfections in the i q signal path
Imperfections in the I/Q Signal Path

PCB and Layout mismatches

Offsets within the dual channel ADC

Component mismatches

back to basics euler s formulas
Back to Basics : Euler’s Formulas
  • Sin 0t is 90 out of phase with respect to cos0t
  • With perfect amplitude and phase matching the signal content at

- 0 cancels

amplitude and phase mismatch
Amplitude and Phase Mismatch
  • Amplitude Mismatch
  • Phase Mismatch

Desired Signal

Image

what is causing the poor quality of this demodulated constellation
What is causing the poor quality of this demodulated Constellation?
  • Very poor LO Quadrature Phase Split (in DMOD)
  • DC Offset of the complete constellation (probably LO to RF Leakage)
  • Noise has enlarged the footprint of the constellation points (poor Receiver Noise Figure)

Symbol

Decision

Threshold

If the symbol lands

on the edge or outside

of the box, bit errors will occur

effects of i q mismatch
Effects of I/Q Mismatch

** Images Occupy BW **

** Interfere with Desired Signal **

Desired Signal

Gain Error

Phase Error

Ideal

Ideal

** EVM Degradation **

dc offset and quadrature error correction
DC Offset and Quadrature Error Correction
  • DC offset and quadrature error correction implemented digitally at the end of the receive chain
    • Most efficient approach in order to compensate for all potential mismatches or errors in the signal path
  • DC Correction
    • If DC free coding is used, a notch filter can be applied
  • Quadrature Error Correction
    • Gain Correction
        • Calculate I^2 – Q^2 to determine the power difference between I and Q.
        • The power difference should be driven to zero.
    • Phase Correction
        • Perform a cross-multiply between I and Q.
        • Can be viewed as a Mixer. The DC term is proportional to the phase difference between I and Q.
        • By definition this should be zero if they are perfectly orthogonal.
ad9262 direct conversion rx signal chain
AD9262: Direct Conversion RX Signal Chain
  • Discrete signal chain targeting Multi-Carrier base stations.
    • WCDMA, CDMA2000, TDSCDMA, WiMax, LTE
  • ADL5523: 400 MHz to 4 GHz Low Noise Amplifier
  • ADL5382: 700 MHz to 4 GHz Quadrature Demodulator
  • AD9262: 16-bit Dual Continuous Time Sigma-delta ADC
    • Integrated DC and Quadrature Error Correction
ad9269 direct conversion rx signal chain
AD9269: Direct Conversion RX Signal Chain
  • Discrete signal chain targeting Multi-Carrier base stations.
    • WCDMA, CDMA2000, TDSCDMA, WiMax, LTE
  • ADL5523: 400 MHz to 4 GHz Low Noise Amplifier
  • ADL5382: 700 MHz to 4 GHz Quadrature Demodulator
  • AD9269: 16-bit Dual Pipeline ADC
    • Integrated DC and Quadrature Error Correction
cw single tone
CW Single Tone

QEC Disabled

  • DC Power: -46.4 dB
  • Image Rejection: 58.5 dB
  • QEC Enabled
  • DC Power: -100 dB
  • Image Rejection: 112 dB
wcdma carrier with gsm blocker
WCDMA Carrier with GSM Blocker
  • GSM blocker 10 MHz away from WCDMA carrier
  • At the antenna, blocker power: -25 dBm and WCDMA carrier: -50 dBm

QEC Disabled

  • DC Power: -46.8 dB
  • Image Rejection: 60.8 dB
  • QEC Enabled
  • DC Power:
  • Image Rejection: 99.2 dB
wcdma carrier with modulated blocker
WCDMA Carrier with Modulated Blocker
  • Blocker 10 MHz away from WCDMA carrier
  • At the antenna, blocker power: -40 dBm and WCDMA carrier: -60 dBm

QEC Disabled

  • DC Power: -46.9 dB
  • Image Rejection: 56.7 dB
  • QEC Enabled
  • DC Power: -105 dB
  • Image Rejection: 63.2 dB
summary
Summary
  • Direct conversion or homodyne receivers have there own merits and challenges.
  • Gain, phase, and offset errors are a few of the challenges that can be addressed with quadrature error correction algorithms
      • Gain, phase, and offset errors cause degradations in receiver EVM and sensitivity
      • Quadrature error correction will improve EVM and sensitivity
  • Direct conversion offers advantages in power, cost and performance over IF sampling architectures
  • Quadrature error correction enables realizable direct conversion solutions for macro level basestations
  • Analog Devices’ first generation of QEC is available integrated into the following products
    • AD9262 – dual 16b continuous time sigma delta ADC
    • AD9269 – dual 16b pipeline ADC
ad9262 16 bit 2 5 5 10mhz 30 160msps dual continuous time sigma delta adc
AD9262 16-Bit, 2.5/5/10MHz, 30-160MSPSDual Continuous Time Sigma Delta ADC

KEY FEATURES

  • SNR: 84.5 dBFS to 10 MHz input
  • SFDR: 87 dBc to 10 MHz input
  • Noise Figure: 15dB
  • Power: 675 mW
  • Sample rate converter: 30-160 MSPS
  • Selectable bandwidth:
    • 5/10/20MHz complex
  • Passive input network
    • No ADC driver amplifier
  • Alias immune
    • No Anti-Alias Filter
  • Integrated Funtions:
    • Decimation filter and Sample Rate Conv.
    • Quadrature Error and DC offset correction
    • PLL clock multiplier
    • Low drift voltage reference
  • Serial Control Interface
  • 1.8 V Analog supply
ad9269 16 bit 20 40 65 80 msps 1 8v dual adc
AD9269 : 16-Bit, 20/40/65/80 MSPS 1.8V DUAL ADC

KEY BENEFITS

  • Total Power Dissipation = 125 mW / ch @80Msps
  • Outstanding Performance
    • SNR = 77 dBFs @ fIN = 40 MHz @ 80 MSPS
    • ENOB of 12.4 @ fIN = 40 MHz @ 80 MSPS
    • SFDR = 88 dBFs @ fIN = 40 MHz @ 80 MSPS
  • Excellent Linearity
    • DNL = ±0.7 LSB (Typical)
    • INL = ±5.5 LSB (Typical)
  • 1.8V or 3.3V CMOS outputs
  • 650 MHz Full Power Analog Bandwidth
  • 1Vp-p to 2Vp-p Input Voltage Range
  • Data Clock Output Provided
  • User Controls via Serial port interface
    • Output Data Format and Mux’d Options
    • Clock Duty Cycle Stabilizer
    • Output Test patterns
    • Analog input range adjustment
    • Power down modes
    • Quadrature Error Correction
  • 16-bit and 14-bit Pin Compatible family
    • AD9268-125 (16-bit), AD9258-125 (14-bit)
    • AD9251 (14-bit), AD9231 (12-Bit), AD9204 (10-bit)