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Integrated Circuit Technology. EE40 6 August 2008. Integrated Circuit Fabrication. Goal: Mass fabrication ( i.e. simultaneous fabrication) of many “chips”, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors. Methods for Top Down processing:

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slide3

Integrated Circuit Fabrication

Goal:

Mass fabrication (i.e. simultaneous fabrication) of many “chips”, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistors

  • Methods for Top Down processing:
    • Addition of material
    • Subtraction of unwanted material
    • Thermal/Doping modification of material

Analogous to making Gingerbread men… yeah.

slide4

Still in Infancy: Bottom-up Processing

Cheap electronics

Organic Printed Electronics – Process is serial (slow) and resolution is poor

High-performance transistors

Catalyzed Growth – Nanotubes/Nanowires hard to place and grow in the desired direction.

slide5

Standard Materials Set

  • Si substrate – selectively doped in various regions
  • SiO2 insulator – MOST IMPORTANT component
  • Polycrystalline silicon – used for the gate electrodes
  • Metal contacts and wiring
si substrates wafers
Si Substrates (Wafers)

Why are wafers round?

We pull crystalline-Si out of hot ingots, starting with a seed crystal.

Crystalline-Si exhibits the best electronic properties for transistors.

300 mm

Typical wafer cost: $50 (!!!)

Sizes: 150 mm, 200 mm, 300 mm diameter

“notch” indicates

crystal orientation

doping

Doping

Makes the Silicon N-type or P-type

adding dopants into si
Adding Dopants into Si

Suppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an “ion gun” called an ion implanter, into the surface of the wafer.

Eaton HE3

High-Energy

Implanter,

showing the

ion beam

hitting the

end-station

Typical implant energies are in the range 1-200 keV. After the ion implantation, the wafers are heated to a high temperature (~1000oC). This “annealing” step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites.

ion implanter
Ion Implanter

translational

motion

e.g. AsH3 gaseous source

As+, AsH+, H+, AsH2+

analyzer magnet

F = q( v B )

Ion

source

Energy: 1 to 200 keV

Dose: 1011 to1016/cm2

Inaccuracy of dose: <0.5%

Nonuniformity: <1%

Throughput: ~60 wafers/hr

ion beam

resolving aperture

accelerator

As+

wafer

spinning wafer

holder

dopant diffusion
Dopant Diffusion

dopant atom

concentration

(logarithmic

scale)

as-implanted profile

depth, x

The implanted depth-profile of dopant atoms is peaked.

In order to achieve a more uniform dopant profile, high-temperature annealing is used to diffuse the dopants

Dopants can also be directly introduced into the surface of a wafer by diffusion (rather than by ion implantation) from a dopant-containing ambient or doped solid source

annealing

Annealing

Fixes the damage caused by ion implantation.

rapid thermal annealing rta
Rapid Thermal Annealing (RTA)

Sub-micron MOSFETs need ultra-shallow junctions (xj<50 nm)

 Dopant diffusion during “activation” anneal must be minimized

    • Short annealing time (<1 min.) at high temperature is required
  • Ordinary furnaces (e.g. used for thermal oxidation and CVD) heat and cool wafers at a slow rate (<50oC per minute)
  • Special annealing tools have been developed to enable much faster temperature ramping, and precise control of annealing time
    • ramp rates as fast as 200oC/second
    • anneal times as short as 0.5 second
    • typically single-wafer process chamber:
rapid thermal annealing tools
Rapid Thermal Annealing Tools

Furnace RTA

Lamp RTA

A.T. Fiory, Proc. RTP2000

  • There are 2 types of RTA systems:
    • Furnace-based
      • steady heat source + fast mechanical wafer transport
    • Lamp-based
      • stationary wafer + time-varying optical output from lamp(s)
film growth

Film Growth

Allows formation of high-quality films (usually SiO2) necessary for low leakage.

formation of insulating films
Formation of Insulating Films

Applied Materials low-pressure chemical-vapor deposition (CVD) chamber

ASM A412

batch

oxidation

furnace

  • The favored insulator is pure silicon dioxide (SiO2).
  • A SiO2 film can be formed by one of two methods:
    • Oxidation of Si at high temperature in O2 or steam ambient
    • Deposition of a silicon dioxide film
thermal oxidation
Thermal Oxidation

oxide

thickness

time, t

or

  • Temperature range:
    • 700oC to 1100oC
  • Process:
    • O2 or H2O diffuses through SiO2 and reacts with Si at the interface to form more SiO2
  • 1 mm of SiO2 formed consumes ~0.5 mm of Si

“wet” oxidation

“dry” oxidation

example thermal oxidation of silicon
Example: Thermal Oxidation of Silicon

99 mm thick Si, with 1 mm SiO2 all around  total thickness = 101 mm

101mm

99mm

Silicon wafer, 100 mm thick

Thermal oxidation grows SiO2 on Si, but it consumes Si, so the wafer gets thinner. Suppose we grow 1 mm of oxide:

oxidation rate dependence on thickness
Oxidation Rate Dependence on Thickness

Note the 0.04mm step in the Si surface!

SiO2 thickness = 1.02 mm

SiO2 thickness = 0.1 mm

SiO2 thickness = 1 mm

Si

  • The thermal oxidation rate slows with oxide thickness.

Consider a Si wafer with a patterned oxide layer:

Now suppose we grow 0.1 mm of SiO2:

selective oxidation techniques
Selective Oxidation Techniques

Window Oxidation

Local Oxidation (LOCOS)

deposition

Deposition

Allows you to put down conformal films that cannot be grown from the substrate.

chemical vapor deposition cvd of sio 2
Chemical Vapor Deposition (CVD) of SiO2

or

“LTO”

“TEOS”

  • Temperature range:
    • 350oC to 450oC for silane
    • ~700oC for TEOS
  • Process:
    • Precursor gases dissociate at the wafer surface to form SiO2
    • No Si on the wafer surface is consumed
  • Film thickness is controlled by the deposition time

oxide

thickness

time, t

conformality
Conformality
  • CVD Properties:
  • Can be deposited on top of anything.
  • Can follow ups & downs (topography) of pre-existing layers
lithographic patterning

Lithographic Patterning

Film-camera-like process that lets you define shapes in your thin films.

patterning the layers
Lithography refers to the process of transferring a pattern

to the surface of the wafer

Equipment, materials, and processes needed:

A mask (for each layer to be patterned) with the desired pattern

A light-sensitive material (called photoresist) covering the wafer so as to receive the pattern

A light source and method of projecting the image of the mask onto the photoresist (“printer” or “projection stepper” or “projection scanner”)

A method of “developing” the photoresist, that is selectively removing it from the regions where it was exposed

Patterning the Layers

oxidation

deposition

ion implantation

etching

lithography

Planar processing consists of a sequence of

additive and subtractive steps with lateral patterning

photoresist exposure
A glass mask with a black/clear pattern is used to expose a wafer coated with ~1 m thick photoresistPhotoresist Exposure

Image of mask appears here

(3 dark areas,

4 light areas)

UV light

Mask

Lens

Mask image is demagnified by nX

photoresist

Si wafer

“10X stepper”

“4X stepper”

“1X stepper”

Areas exposed to UV light are susceptible to chemical removal

exposure using stepper tool
Exposure using “Stepper” Tool

field size increases

with technology

generation

scribe line

1

2

wafer

images

Translational

motion

photoresist development
Photoresist Development

photoresist

Exposed areas of

Developed

photoresist

Solutions with high pH dissolve the areas which were exposed to UV light; unexposed areas are not dissolved

lithography example
Lithography Example
  • Mask pattern (on glass plate)

A

A

B

B

(A-A and B-B)

Look at cuts (cross sections) at various planes

a a cross section
“A-A” Cross-Section

mask

pattern

resist

0

0

1

1

2

2

3

3

4

4

5

5

m

m

[

[

m]

m]

x

x

resist after development

0

1

2

3

4

5

m

[

m]

x

The resist is exposed in the ranges 0 < x < 2 m & 3 < x < 5 m:

The resist will dissolve in high pH solutions wherever it was exposed:

pattern transfer by etching
Pattern Transfer by Etching

We have exposed mask pattern, and developed the resist

photoresist

First: pattern photoresist

Si

oxide etchant … photoresist is resistant.

SiO

2

Next: Etch oxide

etch stops on silicon (“selective etchant”)

Last: strip resist

only resist is attacked

In order to transfer the photoresist pattern to an underlying film, we need a “subtractive” process that removes the film, ideally with minimal change in the pattern and with minimal removal of the underlying material(s)

  • Selective etch processes (using plasma or aqueous chemistry)

have been developed for most IC materials

Jargon for this entire sequence of process steps: “pattern using XX mask”

photolithography
Photolithography

quartz plate

chromium

  • 2 types of photoresist:
    • positive tone:
      • portion exposed to light will be dissolved in developer solution
    • negative tone:
      • portion exposed to light will NOT be dissolved in developer solution

from Atlas of IC Technologies by W. Maly

projection printing considerations
Projection Printing Considerations

Intel’s Lithography Roadmap

minimum feature size lm:

Small lm is desired!

depth of focus
Depth of Focus

depth of focus Dz :

Large Dz is desirable.

etching

Etching

Remove material that you don’t want

etching ion vs wet
Etching: Ion vs. Wet

from Atlas of IC Technologies by W. Maly

  • better etch selectivity
  • better control of etched feature sizes
rie based stringers spacers
RIE-based Stringers / Spacers

Leftover material must be removed by overetching

example process flow

Example Process Flow

CMOS Technology

cmos technology
CMOS Technology

oxide

p+

p+

p-well

n+

n+

n-type Si

  • Challenge: Build both NMOS & PMOS transistors
  • on a single silicon chip
    • NMOSFETs need a p-type substrate
    • PMOSFETs need an n-type substrate
    •  Requires extra process steps!
conceptual cmos process flow
Conceptual CMOS Process Flow

oxide

p+

p+

n+

n+

n-type wafer

*Create “p-well”

p-well

n-type Si

Grow thick oxide

*Remove thick oxide in transistor areas (“active region”)

Grow gate oxide

Deposit & *pattern poly-Si gate electrodes

Grow thick oxide

*Remove thick oxide in transistor areas (“active region”)

*Dope n channel source and drains (need to protect PMOS areas)

*Dope p-channel source and drains (need to protect NMOS areas)

Deposit insulating layer (oxide)

*Open contact holes

Deposit and *pattern metal interconnects

  • At least 3 more masks, as

compared to NMOS process

additional process steps required for cmos
Additional Process Steps Required for CMOS

Cross-sectional view of wafer

Top view of p-well mask

(dark field)

boron

SiO2

n-type Si

1. Well Formation

p-well

  • Before transistor fabrication, we must perform the following process steps:
    • grow oxide layer; pattern oxide using p-well mask
    • implant phosphorus; anneal to form deep p-type regions
2 masking the source drain implants
2. Masking the Source/Drain Implants

“Select p-channel”

“Select n-channel”

boron

photoresist

oxide

p+

p+

p-well

n+

n+

n-type Si

We must protect the n-channel devices during the boron implantation step, and

We must protect the p-channel devices during the arsenic implantation step

Example: Select p-channel

forming body contacts
Forming Body Contacts

oxide

p+

p+

p-well

n+

n+

n+

p+

n-type Si

Modify oxide mask and “select” masks:

Open holes in original oxide layer, for body contacts

Include openings in select masks, to dope these regions

select masks
Select Masks

N-select:

oxide

p-well

n+

n+

n+

n-type Si

P-select:

oxide

p+

p+

p-well

n+

n+

n+

p+

n-type Si

example mems flow

Example MEMS Flow

Micro Electro Mechanical Systems

slide47

MEMS Switch

Source

Drain

Gate(s)

Drain

  • Contact Areas: 0.4x0.4 um2 to 8x8 um2
  • Devices from 50 um to 250 um long
process flow
Process Flow

Elec0 Layer

Isolation

Si Substrate

Pattern Elec0

Main Sacrificial (LTO)

Dimple hole

Pre-alignment

Isolation Growth

6000A Low Temp Oxide

1000A Stoichiometric Silicon Nitride

Poly 0 Deposition

Poly 0 Formation

RIE to isolation w/ overetch

Main Sacrificial Deposition

5500A Low Temp Oxide

Dimple Formation

DRIE to Isolation or timed DRIE

slide49

Fine refill sacrificial (HTO)

Anchor holes

Elec1 Layer

Sacrificial Release

Process Flow

Fine Sacrificial Deposition

650A High Temp Oxide

Anchor Formation

DRIE to isolation layer

Poly 1 Deposition

5500A @ 615C n-doped

Poly 1 Formation

RIE etch to Main Sac

Sacrificial Release

HF:HCl 20’ then critical pt. dry

Process Finished