Sign-Magnitude Representation

1. Sign-Magnitude Representation High order bit is sign: 0 = positive (or zero), 1 = negative Low order bits represent the magnitude: 0 (0002) thru 7 (1112) Number range for n bits = ± (2n-1) Two representations for 0

2. Sign-Magnitude Representations Addition and Subtraction of Numbers • 1- Both operands have same sign: • Result sign bit is the same as the • operands' sign 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1100 1011 1111 • 2- Operands have different sign: • Operation is subtraction. • Sign of result depends on sign of • number with the larger magnitude • R = X-Y • if X>Y subtract |Y| from |X|, • sign(R) = sign(X). • if X<Y subtract |X| from Y|, • sign(R) = sign(Y). 4 - 3 1 0 100 1 011 0 001 - 4 + 3 -1 1 100 0 011 1 001

3. Disadvantages of Sign-Magnitude Representation: Cumbersome addition/subtraction Must compare magnitudes to determine sign of result Definitions N is positive number, then N is its negative 1's complement 4 2 = 10000 -1 = 00001 1111 2 = 10000 -7 = 00111 1000 4 Ones Complement Representation Ones Complement Representation: n N = (2 - 1) - N Example: 1's complement of 7 = -1 in 1's comp. Shortcut method: simply compute bit wise complement 0111 --> 1000 = -7 in 1's comp.

4. Subtraction implemented by addition using 1's complement Still two representations of 0! This causes some problems Some complexities in addition Ones Complement Representation

5. Only one representation for 0 One more negative number than positive number Two Complement Representations N* =2’s comp of N N* = 2n - N Similar to 1's complement except shifted by one position clockwise

6. Two Complement Representations n N* = 2 - N 4 2 = 10000 7 = 0111 1001 = repr. of -7 sub Example: Twos complement of 7 4 2 = 10000 -7 = 1001 0111 = repr. of 7 Example: Twos complement of -7 sub Shortcut method: Twos complement = bitwise complement + 1 0111 -> 1000 + 1 -> 1001 (representation of -7) 1001 -> 0110 + 1 -> 0111 (representation of 7)

7. Number Systems Ones Complement Calculations Add carry-out of sign-bit to LSB (assuming no overflow) 4 + 3 7 0100 0011 0111 -4 + (-3) -7 1011 1100 10111 1 1000 Method: 1- Add two n-bit numbers starting from LSB 2- If there is an end carry (into position n+1), then remove carry and add a 1 to the LSB (end-around carry). End around carry 4 - 3 1 0100 1100 10000 1 0001 -4 + 3 -1 1011 0011 1110 End around carry

8. 4 - 3 1 0100 1100 10000 1 0001 -4 + (-3) -7 1011 1100 10111 1 1000 Number Systems Ones Complement Calculations Why does end-around carry work? Its equivalent to subtracting 2n and adding 1 (i.e. performing -2n+1) Case 1 (M > N): S = M - N = M + N = M + (2n - 1 - N) = (M - N) + 2n - 1 After end-around carry SUM = S -2n+1= (M - N) + 2n - 1 - 2n+ 1 = M - N Case 2 (-M-N, where M + N < 2n-1); -M + (-N) = M + N = (2n - M - 1) + (2n - N - 1) = 2n + [2n - 1 - (M + N)] - 1 after end around carry: = 2n - 1 - (M + N) this is the correct form for representing -(M + N) in 1's complement

9. -4 + (-3) -7 1100 1101 11001 4 - 3 1 0100 1101 10001 Number Systems Twos Complement Calculations 4 + 3 7 0100 0011 0111 Method (If no overflow): 1- Add two n-bit numbers starting from LSB 2- Discard the carry out of the sign-bit. • Overflow condition for • 2’s complement: • if carry into sign-bit differs from • carry out of sign-bit then • the results is an overflow -4 + 3 -1 1100 0011 1111 Simpler addition scheme makes twos complement the most common choice for integer number systems within digital systems

10. 4 - 3 1 0100 1101 10001 -4 + (-3) -7 1100 1101 11001 Number Systems Twos Complement Calculations Discarding End Carry: is equivalent to subtracting 2n Case 1 (-M+N, where N > M): S = -M + N = M* + N = (2n - M) + N = 2n - (N - M) After discarding end carry SUM = S -2n = 2n - (N - M) - 2n = N - M Case 2 (-M + (-N), where M + N < 2n-1): S = -M + (-N) = M* + N* = (2n - M) + (2n - N) = 2n - (M+N) + 2n After discarding end carry SUM = S -2n = 2n - (M+N) + 2n - 2n = 2n - (M+N) = (M+N)*

11. -1 -1 +0 +0 -2 -2 1111 0000 +1 1111 0000 +1 1110 1110 0001 0001 -3 -3 +2 +2 1101 1101 0010 0010 -4 -4 1100 +3 1100 +3 0011 0011 -5 -5 1011 1011 0100 +4 0100 +4 1010 1010 -6 -6 0101 0101 +5 +5 1001 1001 0110 0110 -7 -7 +6 +6 1000 0111 1000 0111 -8 -8 +7 +7 -7 - 2 = +7 5 + 3 = -9 Overflow Conditions (2’s Complement) Overflow occurs when the result of adding two positive (or two negative) n-bit numbers requires more than n bits to be expressed correctly. Overflow indications: Adding two positive numbers results in a negative number Adding two negative numbers results in a positive number

12. Overflow Examples 0 1 1 1 0 1 0 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 5 3 -8 -7 -2 7 Overflow Overflow 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 0 0 5 2 7 -3 -5 -8 No overflow No overflow Simple Check: Overflow occurs when carry into sign-bit does not equal the carry out of the sign-bit.

13. Logic Circuits for Binary Addition With twos-complement numbers, adders can perform both addition and subtraction. Half Adder Circuit Half-adder Schematic

14. Logic Circuits for Binary Addition Full Adder Cascaded Multi-bit Adder usually interested in adding more than two bits this motivates the need for the full adder