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# Magnitude Comparator - PowerPoint PPT Presentation

Magnitude Comparator. Module M5.2 Section 6.1. 4-Bit Equality Detector. A[3..0]. Equality Detector. A_EQ_B. B[3..0]. Magnitude Comparator. A_LT_B. A[3..0]. Magnitude Detector. A_EQ_B. B[3..0]. A_GT_B. Magnitude Comparator. How can we find A_GT_B?.

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### Magnitude Comparator

Module M5.2

Section 6.1

A[3..0]

Equality

Detector

A_EQ_B

B[3..0]

A_LT_B

A[3..0]

Magnitude

Detector

A_EQ_B

B[3..0]

A_GT_B

How can we find A_GT_B?

How many rows would a truth table have?

28 = 256!

Find A_GT_B

Because A3 > B3

i.e. A3 & !B3 = 1

If A = 1001 and

B = 0111

is A > B?

Why?

Therefore, one term in the

logic equation for A_GT_B is

A3 & !B3

A_GT_B = A3 & !B3

# …..

Because A3 = B3 and

A2 > B2

i.e. C3 = 1 and

A2 & !B2 = 1

If A = 1101 and

B = 1011

is A > B?

Why?

Therefore, the next term in the

logic equation for A_GT_B is

C3 & A2 & !B2

A_GT_B = A3 & !B3

# C3 & A2 & !B2

# …..

Because A3 = B3 and

A2 = B2 and

A1 > B1

i.e. C3 = 1 and C2 = 1 and

A1 & !B1 = 1

If A = 1010 and

B = 1001

is A > B?

Why?

Therefore, the next term in the

logic equation for A_GT_B is

C3 & C2 & A1 & !B1

A_GT_B = A3 & !B3

# C3 & A2 & !B2

# C3 & C2 & A1 & !B1

# …..

Because A3 = B3 and

A2 = B2 and

A1 = B1 and

A0 > B0

i.e. C3 = 1 and C2 = 1 and

C1 = 1 and A0 & !B0 = 1

If A = 1011 and

B = 1010

is A > B?

Why?

Therefore, the last term in the

logic equation for A_GT_B is

C3 & C2 & C1 & A0 & !B0

A_GT_B = A3 & !B3

# C3 & A2 & !B2

# C3 & C2 & A1 & !B1

# C3 & C2 & C1 & A0 & !B0

Find A_LT_B

A_LT_B = !A3 & B3

# C3 & !A2 & B2

# C3 & C2 & !A1 & B1

# C3 & C2 & C1 & !A0 & B0

MODULE magcomp4

TITLE '4-BIT COMPARATOR, R. Haskell, 9/21/02‘

DECLARATIONS

" INPUT PINS "

A3..A0 PIN 6,7, 11, 5;

A = [A3..A0];

B3..B0 PIN 72, 71, 66, 70;

B = [B3..B0];

" OUTPUT PINS "

A_EQ_B PIN 36;

A_LT_B PIN 37;

A_GT_B PIN 35;

C3..C0 NODE;

C = [C3..C0];

EQUATIONS

C = !(A \$ B);

A_EQ_B = C0 & C1 & C2 & C3;

A_GT_B = A3 & !B3

# C3 & A2 & !B2

# C3 & C2 & A1 & !B1

# C3 & C2 & C1 & A0 & !B0;

A_LT_B = !A3 & B3

# C3 & !A2 & B2

# C3 & C2 & !A1 & B1

# C3 & C2 & C1 & !A0 & B0;

test_vectors ([A, B] -> [A_EQ_B, A_LT_B, A_GT_B])

[0, 0] -> [1, 0, 0];

[2, 5] -> [0, 1, 0];

[10, 12] -> [0, 1, 0];

[7, 8] -> [0, 1, 0];

[4, 2] -> [0, 0, 1];

[6, 6] -> [1, 0, 0];

[1, 7] -> [0, 1, 0];

[5, 13] -> [0, 1, 0];

[12, 0] -> [0, 0, 1];

[6, 3] -> [0, 0, 1];

[9, 9] -> [1, 0, 0];

[12, 13] -> [0, 1, 0];

[7, 0] -> [0, 0, 1];

[4, 1] -> [0, 0, 1];

[3, 2] -> [0, 0, 1];

[15, 15] -> [1, 0, 0];

END

20

P>Q

Vcc

1

16

2

19

B3

Vcc

P0

P=Q

2

15

3

18

A<Bin

A3

Q0

Q7

3

14

4

17

B2

A=Bin

P1

P7

4

13

5

16

A>Bin

A2

Q1

Q6

5

12

6

15

A1

A>Bout

P2

P6

6

11

7

14

A=Bout

B1

Q2

Q5

7

10

8

13

A<Bout

A0

P3

P5

8

9

9

12

GND

B0

Q3

Q4

10

11

GND

P4

74LS85

74LS682

TTL Comparators

20

P>Q

Vcc

2

19

P0

P=Q

3

18

Q0

Q7

4

17

P1

P7

5

16

Q1

Q6

6

15

P2

P6

7

14

Q2

Q5

8

13

P3

P5

9

12

Q3

Q4

10

11

GND

P4

74LS682

Question

P_GT_Q

P_EQ_Q

P_LT_Q

Draw a logic circuit for

what is in the green box.