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Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell. IEEE International Symposium on Circuits and Systems. May 25-28 th , 2003. Janusz A. Starzyk Ohio University. Russell P. Mohn Sarnoff Corporation. Ohio University School of Electrical Engineering and Computer Science.

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cost oriented design of a 14 bit current steering dac macrocell

Cost-Oriented Design of a 14-bit Current Steering DAC Macrocell

IEEE International Symposium on Circuits and Systems

May 25-28th, 2003

Janusz A. Starzyk

Ohio University

Russell P. Mohn

Sarnoff Corporation

Ohio University

School of Electrical Engineering and Computer Science

outline
Outline
  • Introduction
  • Statistical Yield Model
  • Reduction of Systematic Errors
  • Design Cost Consideration
  • DAC Implementation
  • Conclusion and Future Work
introduction
Introduction
  • Design Consideration based On the Statistical Model
  • Current Source Analysis
  • Reference Circuit Design and Analysis
  • Spreading of the Composite Transistors and Random Walk
  • Thermometer Circuit Design
  • Glitches and Dynamic Performance
  • Architectures and Layout
  • Top Level Simulation Results
  • Estimated Design Performance
organization
Organization
  • The DNL and INL Specifications
  • Design Consideration based On the Statistical Model
  • Segmentation of the Composite Transistors and Random Walk
  • Glitches and Dynamic Performance
  • Architectures and Layout
  • Simulation Results
  • Summary and Estimated Design Performance Figures
dnl standard deviation
DNL standard deviation
  • for the segmented architecture
  • B=4, so to meet the requirements for DNL
segmentation of the composite transistors and random walk
Segmentation of the Composite Transistors and Random Walk
  • depends on the transistor area A and spacing D as
  • where A, AVTand S are process related constants
segmentation of the composite transistors and random walk1
Segmentation of the Composite Transistors and Random Walk
  • The random errors are determined by mismatch
  • The systematic errors are determined by process, temperature, and electrical gradients
  • In optimally designed DAC the INL and DNL errors depend only on the random errors level
  • Increasing transistor area reduces the random errors.
  • The systematic errors are layout-dependent and are minimized by transistor switching scheme.
random errors unit transistor requirements
Random errors - unit transistor requirements
  • The minimum area of the unit transistor

Parameters A and AVT are technology dependent

the level of systematic errors
The Level of Systematic Errors
  • where k=Acell /A>1 is a current cell layout coefficient with Acell -unit current cell area
current source matching vs the design area for 12 bit dac
Current-source Matching vs. the Design Area for 12 bit DAC

Green line indicates

the effect of

systematic errors

current source analysis uneven output voltage
Current Source Analysis uneven output voltage

Iout1=13.33mA, Iout2=0 mA, Vout1=1V, Vout2=0 V

current source analysis uneven output voltage1

dI

Ioff

Current Source Analysis uneven output voltage

In order to achieve satisfactory INL level

we must keep the cut-off current low

Vd src

So the cut-off current is limited by

Vd c

Vout1

Vout2

Io

current source analysis even output voltage
Current Source Analysis even output voltage

Iout1=Iout2=6.66 mA, Vout1=Vout2=0.5V

slide17

Reference Resistor and Output Current

The following empirical

relation holds for Iout<20mA

layout specifications of the 12 bit dac
Layout specifications of the 12-bit DAC
  • DAC is built as a segmented architecture with 8-bit thermometer and 4-bit binary sections (to lower the glitches)
  • LSB cell area (1/4 of unary source cell) is A=308 m2 with W=17 m and L=18 m
  • 8-bit thermometer decoder is designed in two groups- one with 3 thermometer bits and second with 5 bits (MSBs)
  • Random walk is implemented with derived permutation sequence to minimize systematic errors
  • Symmetrical layout, synchronization of control signals, synchronization of unary and binary current source transistor switching, and the cascode structure of the unit current sources control dynamic performance.
spreading of the composite transistors and random walk
Spreading of the Composite Transistors and Random Walk
  • The random errors are determined by mismatch
  • The systematic errors are determined by process, temperature, and electrical gradients
  • In optimally designed DAC the INL and DNL errors depend only on the random errors level
  • Increasing transistor area reduces the random errors.
  • The systematic errors are layout-dependent and are minimized by transistor switching scheme.
reduction of linear systematic errors
Reduction of Linear Systematic Errors
  • To compensate for linear errors a symmetrical splitting is required
  • Each transistor will be split into 4 locations
wiring via placement in current sources
Wiring - via Placementin Current Sources

Current sources are connected to horizontal wires sequentially

slide30

Layout

  • Signal S2(32)
    • Large capacitive load
    • Connects 4 symmetrically spread current sources
  • Unary current source 256 turned OFF
slide31

Layout

  • Signals S2(32) and S2(33)
  • Current sources controlled by S2(33) are far away from those controlled by S2(32)
  • Switching sequence designed to minimize systematic errors
slide32

Layout

  • Signals S2(32), S2(33), and S2(34)
glitches
Glitches
  • The glitch current
  • where Agl is the glitch amplitude, tgl is the glitch period, and t0 is the synchronization mismatch (delay time)
dynamic performance
Dynamic Performance
  • For dynamic performance of DAC due to glitches and parasitic effects the following are recommended:
    • synchronize the control signals of the switching transistors;
    • reduce the voltage fluctuation on the drains of the current sources during switching
    • carefully switch the current source transistor on/off
    • reduce coupling of the control signals through lowering the voltage of the power supply of the latches.
    • increase the output resistance in high frequency applications
dynamic performance1
Dynamic Performance
  • The synchronization is achieved by equalizing each latch output load capacitance.
  • Using a large channel length unit current source transistor and tuning the crossing point of the switching control signals such that both switches are never switched off at the same time solves voltage fluctuation at the drain problem
  • Using an additional cascode transistor increases output impedance for high frequency applications
    • This architecture has an additional advantage of lowering glitch energy due to the drain voltage variations of the unit source.
slide36

Layout

  • 1 column (8 rows) of latches
  • Vertical green wires:
    • Latch input from D flip-flops
    • Latch output to current source array
  • Equal load
slide39

Layout

  • Equalizing capacitive load between binary latches and unary latches
  • Load determined by total length of wires to unary current sources

Binary wire

Unary wire

slide49

2^12 Ramp INL & DNL

  • Unbalanced capacitive unary and binary loads
  • INL(2^12) < 10*INL(2^7)
    • 17 days simulation versus 8 hours simulation
terayon load analysis hpads
Terayon Load Analysis (HPADS)

10 MHz signal

10nA (left)

10mA (right)

output of terayon post d a filter1
Output of Terayon post-D/A Filter
  • Cutoff around 80 MHz
  • Limited Resolution
power supply rejection ac analysis1
Power Supply Rejection - AC Analysis

Finally the PSRR depends only on the design voltages

Using the design values

Which agrees with the simulation results

full view of the d a
Full view of the D/A

Noisy digital

Semi-quiet digital

Quiet analog

  • Digital inputs along top
  • Analog inputs/outputs along bottom
  • 1716.5µm x 1700.0 µm
  • Area = 2.918mm2
  • Analog circuitry separated from noisy digital environment
  • Two guard rings
    • 40 µm n-well
    • 100 µm p+
slide61

Full view of the D/A

  • Symmetries about orthogonal axes:
    • Binary Current Sources
    • Unary Current Sources
  • Modular design in both digital and analog sections
  • Digital inputs have at least 4.46 µm separation
  • Reference circuit tightly integrated with sensitive analog circuitry
slide62

Layout

  • 8 Binary inputs DAC_D(4) ... DAC_D(11) encoded in thermometer code
  • D Flip-flop organization
    • 8 rows x 32 columns
  • DAC_D(4) ... DAC_D(6) select 1 of 8 rows
  • DAC_D(7) ... DAC_D(11) select 1 of 32 columns
  • Column select
    • Distributed logic minimizes space
  • Local clock drivers
slide63

Layout

  • Distributed thermometer encoder
  • D flip-flops above latches
  • In black
    • 1 row select
    • 1 column select at C(i) and C(i+1)
slide64

Layout

  • 1 Column (8 rows) of D flip-flops
  • 8 complementary signals carried on vertical green wires
  • local clock driver, column decode logic
slide65

Layout

  • Clock distribution
    • Inverted clk signal to digital input flip-flops
    • clk signal split left/right from center
slide66

Layout

  • Vertical green wires:
    • Routing from D flip-flops to latches
    • Routing from latches to current source array
slide67

Layout

  • Wiring over current source array
    • Comp. signals: S1, S2
    • 32 x 32 wires per quarter unary source
    • Shield in met2, met 5
    • Horizontal in met3
    • Vertical in met4
    • Wire width = 0.22 µm
    • Wire spacing = 1.0 µm
slide68

Salient DAC Specifications

  • Resolution: 12 bits
  • Conversion Rate: 180 MSPS
  • Differential current outputs
    • 20mA at full scale
    • Gain Error: ±10% of full scale
  • DNL: ±1 LSB INL: ±2 LSB
  • Wideband SFDR
    • 1MHz out: 70dBc, … 80MHz out: 50dBc
  • Narrowband SFDR
    • 1MHz out (within ±100 kHz window): 80dBc
  • Max Power: 200mW Power Down: 15uA
  • Trise, Tfall (Cl<10pF, Rl=50): 1.6-2.5ns Trise-Tfall: 0.1-0.2 ns
  • Glitch Energy Error: 2.0-5.0 pV-s