1 / 13

Neeraj Keskar and Gabriel A. Rincón-Mora Analog and Power IC Design Lab

A High Bandwidth, Bypass, Transient-Mode ΣΔ DC-DC Switching Boost Regulator with Wide LC Compliance. Neeraj Keskar and Gabriel A. Rincón-Mora Analog and Power IC Design Lab School of Electrical and Computer Engineering Georgia Institute of Technology 24 May, 2007. Motivation.

myrna
Download Presentation

Neeraj Keskar and Gabriel A. Rincón-Mora Analog and Power IC Design Lab

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A High Bandwidth, Bypass, Transient-Mode ΣΔ DC-DC Switching Boost Regulator with Wide LC Compliance Neeraj Keskar and Gabriel A. Rincón-Mora Analog and Power IC Design Lab School of Electrical and Computer Engineering Georgia Institute of Technology 24 May, 2007

  2. Motivation • IC solution for DC-DC power supplies required to reduce design time, board size, part count, ultimately cost. • However, in most cases filter L, C components are off-chip (because of size) and subject to variations due to application requirements, component tolerances, and drift. • Converter feedback loop response depends on L, C values, hence, limitations in integrating feedback compensation circuit • Niche applications may have on-chip or on-package passives, but for dynamically changing multi-mode converters, effective L, C seen by compensation circuit may vary • Overall, there is a need to have IC solution that will give stable frequency compensation for a wide range of external LC components

  3. Asynchronous Sigma-Delta (SD) Control Block diagram of SD control • Objective: • Regulate z = VREF • Error avg(e) = 0; i.e. IN = avg(u) • It can be shown that: • The above system is ALWAYS stable, • if 0 < IN < 1. • Therefore, any system represented • as above is stable if 0 < IN < 1. e.g. Buck converter 0 < (IN = VOUT/VIN) < 1

  4. SD Control in Boost Converters: 1. Sliding-mode Control • Variable regulated is Vs, which is a combination of IL and VOUT • Variable Vs = RI.(IREF – IL) + KV.(VREF – VOUT) • Control regulates Vs = 0 using SD controller • At DC, IREF = IL, hence if Vs = 0, then VREF = VOUT

  5. Stability Requirements 1. Hence, 2. Bandwidth of the LPF has to be less than that of the converter power stage where, • Drawbacks in designing for variable filter LC values: • Transient response limited by low bandwidth of the LPF in feedback path • Multiple cycle transient response gives further degradation

  6. 2: Dual-loop SD Control Voltage loop Current loop • Inductor current regulated in separate high-frequency loop • Output voltage regulated in low-frequency loop • Both loops controlled through SD controllers, eliminating frequency compensation

  7. Dual-loop SD Control (contd.) • Advantages • Fast transient response only limited by slew rate • of power stage • Wide filter LC compliance • Drawbacks • Higher inductor current lower efficiency • Higher steady-state voltage ripple

  8. Combined Control Strategy Combination of two previous strategies in multi-mode system: Bypass path (Dual-loop SD control) • High bandwidth path • Operated during transient for fast response Main path (Sliding-mode (SD) control) • Low bandwidth path • Operated during steady state for low ripple, high efficiency

  9. Combined Control Strategy (contd.) • Start-up under bypass mode with higher voltage ripple; inductor current higher than that at steady-state value with switch MPP3 switching • Inductor current decreased by mode transition block until steady state; switch MPP3 then stops switching

  10. Mode Transition Block Main-to-bypass transition • In case of a transient, comparator Q3 raises inductor current to peak value in a single step • Output voltage quickly rises to and stays at the desired value with MPP3 switching Bypass-to-main transition • Withswitch MPP3 switching (bypass mode),I1.RF2 adds offset between avg (ILRS) and VIREF • Inductor current therefore decreases until MPP3 stops switching, i.e. circuit enters steady state

  11. Comparison of Load Transient Response Sliding-mode (SD) control, fLPF = 2.7 kHz Combined SD control Both single and combined loop controllers designed to provide stable operation for LC variations: L = 1 to 30 mH, C = 20 to 350 mF • Load step response: ILOAD from 0.1 to 1 A, L = 5 mH, C = 47 mF • Proposed technique gives a DVOUTimprovement of ~ 150 mV (37 %)

  12. Load Transient: Inductor Variations • Maximum improvement at low inductance values (50 % improvement at 1 mH) • Transient response becomes comparable as inductance approaches maximum • design value (30 mH)

  13. Summary • A new multi-mode control strategy was introduced in boost DC-DC converters, combining speed advantages of dual-loop SD control and low steady-state ripple of sliding-mode (SD) control • The strategy enables a de-coupling between the conflicting requirements of greater relative stability and fast transient response • The strategy allows wide variations in LC filter parameters can be accommodated without the use of any external frequency compensation • A fast, single-step (slew-limited) load transient response obtained in the proposed strategy for a wide range of LC filter parameters as against a feedback-bandwidth limited response in conventional control • An optimal boost DC-DC converter control strategy was introduced as most suitable for integration enabling a simple, user-friendly, and effective solution

More Related