Circuits and Analysis

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Circuits and Analysis. DFM = Design for Manufacturing Design for Mass-Production. eCAD Tools. Pspice Freeware Simulator (~6MB download) Includes simple schematic capture & analog simulator http://www.linear.com/designtools/softwareRegistration.jsp.

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Circuits and Analysis
• DFM = Design for Manufacturing
• Design for Mass-Production

Includes simple schematic capture & analog simulator

http://www.linear.com/designtools/softwareRegistration.jsp

http://www.cse.ogi.edu/CFST/tut/help/pspice_examples.html

Current: Sum of the currents at any node must equal 0.

Currents Entering = Currents Exiting

Voltage:Sum of the voltages in a circuit loop must equal 0.

Voltages Supplied = Voltages Dropped

Recall the Basic Kirchhoff’s Circuit Laws

Capacitor Review
• Static Characteristics: C = Q/V
• Where 1 Farad = 1 Coulomb per 1 Volt
• If C is constant and I try to store more charge on C, its voltage will increase proportionally
• If C is constant and I want to increase the voltage across it, I need to add more charge
• Dynamic Characteristics: I(t) = C dV/dt
• where; I(t) = capacitor charging current (Amps)
• dV/dt = capacitor voltage change (Volt/Sec)
• Note: If I(t) is constant, V(t) is a ramping voltage
• Laplace Impedance  1/sC
• Complex Impedance  1/jwC
• Capacitors Add Directly in Parallel Circuit: CEQ = C1 + C2 +…CN
• Capacitors Add Inversely in Series Circuit: CEQ-1 = C1-1 + C2-1 +…CN-1
Dynamic RC Circuit Behavior Review

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Where t = RC (time constant)

Inductor Review
• Static Characteristics: L = Fm/I
• Where 1 Henry = 1 Weber (Mag Flux) per Amp
• Note: 1 Henry = 1 Volt per Amp/Sec = 1 Volt-Sec/Amp
• Dynamic Characteristics: V(t) = L dI/dt
• Where; V(t) = inductor voltage
• dI/dt = inductor current change (Amp/Sec)
• Note: If DC current thru an inductor is abruptly stopped (circuit opened), the induced voltage V(t) will “spike” very high
• Laplace Impedance  sL
• Complex Impedance  jwL
• Inductors Add Directly in Series Circuit: LEQ = L1 + L2 +…LN
• Inductors Add Inversely in Parallel Circuit: LEQ-1 = L1-1 + L2-1 +…LN-1
Parallel Resonance (Infinite Impedance)

Parallel Impedance Z = sL // (sC)-1

Z = (sL)(sC)-1 / (sL + (sC)-1)

Z = sL / (s2LC + 1)  jwL / (-w2LC + 1)

Note Z  Infinity when w2 = LC  w = (LC)-1/2

(f = 2pw )

Series Resonance (Zero Impedance)

Series Impedance Z = sL + (sC)-1

Z = s2LC + 1  -w2LC + 1

Note Z  0 when w2 = LC  w = (LC)-1/2

Electrolytic & Electric Double Layer
• Rolled-Wet electrolyte construction
• Very Polarized, Low Voltage Range
• Ultra High Capacitance Density (5000F available)
• High Cost
• Used in Power Supplies, Power Backup Systems
• Listed on WEEE Restrictions – Item # 15 (2.5x2.5cm)
• Reliability Risk for High Temp or High Vibration Apps
Tantalum
• Solid Dielectric construction
• Polarized
• Medium-High Capacitance Density
• Low Voltage Range
• Used for Board Large (Bulk) Decoupling
• Rectangular SMT package
• Ceramic
• Solid Dielectric construction in single & multilayered
• Non-polarized, High Voltage Range
• Low Capacitance Density
• Low Cost
• Used for IC decoupling, low precision timing, filters
• Rectangular SMT package
Polyester Film, Metalized Polyester Film
• Solid Dielectric construction in multilayered
• Non-polarized, High Voltage Range
• Medium Cost
• Low Capacitance Density
• Used for medium precision timing, filters
• Rectangular SMT packages
• Polypropylene
• Solid Dielectric construction
• Non-polarized, High Voltage Range
• Medium Cost, Low Capacitance Density
• Very Low Leakage
• Used for high precision timing, filters, sample-hold
• Rectangular SMT packages
Inductors
• Air Core , Ferrous Core Stick & Ferrous Core Toroid
• Note: Air Core May Induce Large Stray Fields
• Shielded and Unshielded
• Inductance will Have Resistance
• Thru Hole & SMT packages
• Rated for Inductance, Max Current, Frequency
Passive Components, R-L-C
• Critical Factors:
• Ambient Temperature
• Thermal Deratings & Variation of Primary Parameter (Temp Co)
• Maximum Imposed Voltage and/or Current
• Maximum Imposed dV/dT and/or Frequency
• Inductive Frequency (high frequency model)
• Minimum Analysis & Selection Considerations:
• Primary Parameter Tolerances (R, L, C %)
• Total Power vs Package Dissipation
• Maximum Voltage
• Composition, Specific die-electrics, construction, etc
Passive Discretes
• Resistors/Inductors: Must specify or account for Tolerance, Power, Package and Temp Coefficient
• Derating Guide: ~50% of rated power or current
• Std Tolerances: 0.1%, 1%, 5%, 10% and 20%
• Constructional Anomalies: Max Voltage, Inductive with High Freq
• Capacitors: Must specify or account for Tolerance, WV, Polarization, Dielectric, Temp Co and Package
• Derating Guide: ~50% of rated voltage
• Std Tolerances: 1%, 2%, 5%, 10%, 20%, 80%
• Constructional Anomalies: Charge Leakage, Inductive with High Freq,
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• Amplifiers
Simple Small Signal Models for the BJT

Figure 4.33 Small-signal equivalent circuits for the BJT.

Common Emitter Amplifier & Small Signal Equivalent Circuit

Voltage Gain: Av = vO/vIN = - bAC (RC//RL)

(rp + (1 + bAC)RE1)

Current Gain: Ai = iO/iIN = - bAC RC(R1//R2)/(RC+RL)

(rp + (1 + bAC)RE1) + (R1//R2)

Input Impedance: Ri = vIN/iIN = (R1//R2)//(rp + (1 + bAC)RE1)

VCC/RDC

VCC

DC or Static Load Line:VCC = ICRC + VCEq + (IC + IB)RE Note IC = (bDC)IB & RE = RE1 + RE2

 VCC = IC (RC + RE + RE/ bDC) + VCEq = IC (RDC) + VCEqwhere RDC = RC + RE + RE/ bDC

Now put into the form Y = mX = b where Y = IC & X = VCE

IC = VCE (-RDC )-1 + VCC (RDC )-1    Y intercept = VCC/RDC X intercept = VCC

• AC or Dynamic Load Line:
• VCC = ICq (RDC) + iCq (RAC) + vCE + VCEqwhere RAC = RC//RL + RE1 + RE1/ bAC
• In the form Y = mX + b  IC = VCE (-RAC )-1 + (VCEq/RAC + ICq )
•   Y intercept = VCEq/RAC + ICq X intercept = VCC - ICq (RDC -RAC)

The AC or Dynamic Load Line shows the slope the amplifier will actually operate on with signal swing

Yd

Ys

Q

Xd

Xs

Static: IC = VCE (RDC )-1 + VCC (RDC )-1   Ys = VCC/RDC Xs = VCC

Dynamic: IC = VCE (RAC )-1 + (VCEq/RAC + ICq )   Yd = VCEq/RAC + ICq Xd = VCC - ICq (RDC -RAC)

Quiescent Point Q will be at Intersection, For Best Q Point - Bisect the AC Load Line End Points

Note: For Capacitively Coupled Loads RAC < RDC

Therefore Set ICq = VCC/(RDC + RAC)

General Linear Analog Circuits
• Amplifiers and Attenuators
• Oscillators (sinusoidal)
• Filters
• Voltage Regulators
• Voltage References
General Non-Linear Analog Circuits
• Comparators
• Oscillators (non-sinusoidal, square, sawtooth, etc)
• Voltage Limiters and Clamps
• Rectifiers and Bridges
• Math Functions (multiply, divide)
• Log and other Non-linear Amplifiers
• Sample and Hold Amplifiers
• Envelope & Peak Detectors
• Phase Detectors
• Phased Locked Loops
• Switching Voltage Regulators
Small Signal Amplifiers
• Critical Factors:
• Component Tolerances, particularly gain setting R’s, Transistor B
• OpAmp Input Offset Voltage (Vio), worse for high gain
• Input Bias Current (Ib), Input Offset Current (Iio)
• Output Slew Rate and Output Vp-p at Maximum Frequency
• Typical DFM Analysis:
• Total DC Offset error in Volts (1,2,3)
• Total Gain Error vs Nominal, Converted to Volts (1,4)
• Power Bandwidth for Application (1,5)
Basic Gain in Voltage, Current or CombinationLinear Operation: No New Frequencies Created!
• Voltage Amplifiers (Vin >> Vout): Av = Vout/Vin
• Current Amplifiers (Iin >> Iout): Ai = Iout/Iin
• Transimpedance (Iin >> Vout): Zm = Vout/Iin
• Transconductance (Vin >> Iout): Gm = Iout/Vin

• Input Impedance: Zin = Vin/Iin
• Output Impedance: Zout = {Vout(NL) – Vout(L)}/Iout
• Slew Rate (SR): Min dVout/dT
• Slew Rate BW = SR/2pVp where Vp = Peak Voltage
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Advantages Over Single Ended Amplifier Block ??

• Easy to add positive and negative feedback with differential input
• Single Ended Application Gains can be tightly controlled with external components and made insensitive to internal transistor gain variations
• Inherent noise rejection when noise enters both input terminals
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Operational AmplifierIdeal Assumptions

Vp

Used for basic analysis, nominal gain analysis

Vout

• Vout = Ad (Vp – Vn) where Ad is the diff gain
• Zin = Infinite, Iin = 0 where Iin is the input current
• Vp = Vn because of infinite Ad, Vo may be non-zero under this condition
• Iout = Infinite (Often a false assumption)

These basic assumptions allow simple circuit analysis to determine Nominal gain applications

Vn

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Operational AmplifierPower Supplies

Vcc

Vp

Power Supplies can be a critical consideration

Vout

• -Vcc < Vout < Vcc At all times, Vout(max) may be as low as 2 to 5 volts below Vcc depending upon model
• Vcc, -Vcc sometimes referred to as “Rails” due to power distribution on some boards resembling tracks
• Many applications use “Split” supply Operation
• Split Supply means Vcc = |-Vcc|
• Some models characterized for 1 supply operation (but ALL will work there)
• Single Supply means –Vcc = 0
• Vcc, -Vcc power pins should always be capacitively filtered with 0.1uf (usually ceramic monolithic X7R or similar)

Vn

-Vcc

Operational AmplifierMany Types Available
• Others:
• Video
• Current Feedback
• Power
• Chopper Stabilized
• Electrometer
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Operational AmplifierBasic Applications

Rf

Av = - Rf/Ri

Zin = Ri

Inverting Voltage Amp

Ri

Vin

Vout

Rp

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Operational AmplifierBasic Applications

Ri

Av = 1 + Rf/Rp

Zin = Ri +

Non-Inverting Voltage Amp

When Rf=0, Rp=~Infinite…… Av = 1

Vin

Vout

Rf

Rp

8

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Operational AmplifierBasic Applications

Av = 1

Zin =

Unity Gain Voltage Amp

Vin

Vout

8

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Operational AmplifierBasic Applications

Ri

Gm = 1/Rp

Zin = Ri +

Transconductance Amp

Vin

RL

Iout

Rp

8

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Operational AmplifierBasic Applications

Rf

Zm = - Rf

Transimpedance Amp

Iin

Vout

RL

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Operational AmplifierBasic Applications

Ai = -(1 + Ri/Rp)

Current Amplifier

Iin

RL

Ri

Iout

Rp

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Operational AmplifierIdeal Assumptions

Vp

Used for basic analysis, nominal gain analysis

Vout

• Vout = Ad (Vp – Vn) where Ad is the diff gain
• Zin = Infinite, Iin = 0 where Iin is the input current
• Vp = Vn because of infinite Ad, Vo may be non-zero under this condition
• Iout = Infinite (Often a false assumption)

These basic assumptions allow simple circuit analysis to determine Nominal gain applications

Vn

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Operational AmplifierReal Characteristics

Ip

Vp

Vout

Used for more accurate

Gain Characterization

Iout

Vio

• Vout = Ad(Vp – Vn) + Ac(Vp + Vn)/2 + Vio

Ad is the diff gain, Ac is the common mode gain, Vio = offset voltage

• CMRR = Common Mode Rejection Ratio = 20log(Ad/Ac)
• Ib = Bias Current (Ave Current = [Ip + In]/2)
• Iio = Offset Current (Diff Current = Ip – In)
• Iout = Finite, Split between gain set components and load
• Vio = Input Diff Voltage reflected back from Vo under the condition the Vp = Vn = 0

Use superposition to understand contributions

In

Vn

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Operational AmplifierReal Characteristic Effects

Basic Strategy

Vp

• Consider the Effect Separately, then combine results
• Show Ib and Iio as input current sources
• Show Vio as diff voltage on Vp-Vn
• Use amended opamp in std application circuit, Vin=0 (grounded).
• Find Vout, all Vout will be Verror due to Offset and Bias

Vout

Vn

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Inverting ConfigurationOffset Error Contribution 1

Rf

Ii = (0-Vio)/Ri

If = (Vio-Vo)/Rf

Ii = If

Vo = Vio(1 + Rf/Ri) = Verr

Inverting Voltage Amp

Error Voltage due to Vio

Ri

If

Vout

Vio

Ii

Rp

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Non-inverting ConfigurationOffset Error Contribution 1

Ri

Ii = (0-Vio)/Rp

If = (Vio-Vo)/Rf

Ii = If

Vo = Vio(1 + Rf/Rp) = Verr

Non-Inverting Voltage Amp

Error Voltage due to Vio

Vin

Vout

Vio

Rf

If

Rp

Ii

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Inverting AmplifierOffset Error Contribution 2

Rf

At V+: Iio = Ib + V+/Rp

V+ = Rp(Iio-Ib)

At V-: -V-/Ri = (V--Vout)/Rf + Ib + Iio

Sub V+ into above equation

Vo = Verr = Rf(Ib-/+Iio) - [((RfRp)/Ri + Rp)(Ib+/-Iio)]

Note if Iio = ~0 and Rp = Rf//Ri, then Verr = 0

Verr is always minimized when Rp = ~Rf//Ri

Inverting Voltage Amp

Error Voltage due to Ib, Iio

Ri

If

Vin

Vout

Iio

Ii

Ib

Ib

Rp

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Non-Inverting AmplifierOffset Error Contribution 2

Rf

At V+: Iio = Ib + V+/Ri

V+ = Ri(Iio-Ib)

At V-: -V-/Rp = (V--Vout)Rf + Ib + Iio

Sub V+ into above equation

Vo = Verr = Rf(Ib-/+Iio) - [((RfRi)/Rp + Ri)(Ib+/-Iio)]

Note if Iio = ~0 and Ri = Rf//Rp, then Verr = 0

Verr is always minimized when Ri = Rf//Rp

Non-Inverting Voltage Amp

Error Voltage due to Ib, Iio

Rp

If

Vout

Iio

Ip

Ib

Ib

Ri

Ii

Vin

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Inverting AmplifierGain Error

Rf

Av (nom) = - Rf/Ri

But Assume Vout = Ad(V+ - V-)

Find expressions for V+ & V-

Substitute into above Vout

Solve for Vout/Vin = Av

Av = Av(nom)/CF

CF = Correction Factor

|Av| < |Av (nom)|

Inverting Voltage Amp

Ri

If

Vin

Vout

Ii

Rp

Don’t Forget to Factor in Res Tol% !

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Non-Inverting AmplifierGain Error

Ri

Vin

Vout

Av (nom) = 1+ Rf/Rp

But Assume Vout = Ad(V+ - V-)

Find expressions for V+ & V-

Substitute into above Vout

Solve for Vout/Vin = Av

Av = Av(nom)/CF

CF = Correction Factor

|Av| < |Av (nom)|

Non-Inverting Voltage Amp

Rf

Rp

Don’t Forget to Factor in RTol% !

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Operational AmplifierGain Error

Rf

Ri

If

Vin

Vout

Ii

Largest Error will be due to Rtol !!Gain Error = Av(nom) – Av

Verr from Gain Error

Verr = Vin(max) * Gain Error

Rp

Total Error
• Verr due to Gain Error incl Resistor tolerance
• Verr due to Offset and Bias Effects
• Requirements may dictate an outright nominal gain plus a total error voltage or current budget
10K 5%

0.1V

Vout

10K 1%

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1K

1%

Example
• Find Overall Worst Case DC Error Voltage

Nominal Gain = 1+Rf/Ri = +11.0

Nominal Output = 1.1V

TLO72C

10K 5%

0.1V

Vout

10K 1%

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1K

1%

Analysis requires opamp data sheet info

TLO72C

• TL072C over 0-70C:
• Ib(max) = 7nA
• Iio(max) = 2nA
• Vio(max) = 13mV
• Avo(min) = 15000
10K 5%

0.1V

Vout

10K 1%

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1K

1%

Non-Inverting AmplifierGain Error

Av (nom) = 1+ Rf/Rp = 11.0

Av (min)  Rf down 1%  9.9KW,

Rp up 1%  1.01KW

Av = Av(nom)/CF

CF = Correction Factor

TLO72C

Av(min) = 15K(1.01+9.9) / [(15K)(1.01) + 9.9 + 1.01] = 10.79 Error from nominal = (0.1V)(11.0 – 10.79) = 0.021  21mV

Av(max) = 1 + (10.1 / 0.99) = 11.20 (Assume Ad is max) Error from nominal = (0.1V)(11.20 – 11.0) = 0.020  20mV

Worst Case Gain Error assuming Vin = 0.1V = 20mV or 21mV

10K 5%

0.1V

Vout

10K 1%

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1K

1%

Non-inverting ConfigurationOffset Error Contribution 1

Verr1 = Vio(1 + Rf/Rp)

Verr1a(max) = 13mV(1 + 10.1/0.99) = 145.6mV

Verr1b(max) = 13mV(1 + 9.9/1.01) = 140.4mV

TLO72C

Worst Case Offset 1 Error = 145.6mV or 140.4mV

10K 5%

0.1V

Vout

10K 1%

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1K

1%

Non-Inverting AmplifierOffset Error Contribution 2

Verr2 = Rf(Ib-/+Iio) - [((RfRi)/Rp + Ri)(Ib+/-Iio)]

Verr2 = 10(7nA-/+2nA) – [(10)(10)/1 + 10](7nA+/-2nA)

Verr2 worst case = ~1mV

TLO72C

Worst Case Offset 2 Error = ~1mV

Total Error
• Verr due to Gain Error = 19.0mV
• Verr due to Offset 1 = 145.6mV
• Verr due to Offset 2 = 1mV

Answer: Worst Case Total Error = 165.6mV (when Rf = max, Rp = min)

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Rf

Av = - Rf/Ri = Nominal Closed Loop Gain

Ad (Op-amp) = Open Loop Gain

• Ad rolls off with frequency, 20db/dec, after first pole (~ 1 to 100 Hz)
• Bandwidth of Closed Loop Gain, Fcl, limited by Ad(f)
• Ad(0) = Typically 60dB to 140dB or higher
• When Ad(f) = 1, f = Unity Gain Freq
• Above fcl, Av will fall at 20db/dec (8db/oct)

Ri

Vin

Vout

Rp

Filters
• Critical Factors:
• Passive Component Tolerances
• OpAmp Input Offset Voltage (Vio), worse for high gain
• Input Bias Current (Ib), Input Offset Current (Iio)
• Output Slew Rate and Output Vp-p at Maximum Frequency
• Worst Case Analysis:
• Transfer Function Analysis
• Total DC Offset error in Volts (1,2,3)
• Mag (dB) & Phase (deg) vs Frequency Plots (1,4)
• Power Bandwidth for Application (1,5)
• Pulse Response (topology, 4)
Filter Basics
• Linear Operation Must Be Maintained:
• Gain is Frequency Dependent but ….
• No New Frequencies are Created
Basic Low Pass Filter

Potential Filter Shapes

Basic High Pass Filter

Potential Filter Shapes

Basic BandPass Filter

Potential Filter Shapes

Basic BandStop Filter

Potential Filter Shapes

Filter Basics

General 2nd Order Transfer Function where;

• 2nd order Filter Transfer Function Analysis Shaping:
• Shaping Factor Q aka as Quality Factor
• Q is related to the Damping factor Q = 1/(2a)
• Put Xfer Function into form with D(s) above, Coef of S2 must be 1
• Find expression for Wo by equating coefficient of S0
• Then find Q and/or a by equating coefficient of S1
Effect of Shape Factor on Filters

Lowpass

Highpass

Bandpass

Bandstop

Filter Scaling
• Filter Scaling:
• All filter coefficients and polynomials are normalized to Wo = 1 rad/sec
• To rescale, replace S with S/Wo(new)
• Given an RC implementation circuit, Wo may also be moved by rescaling the Capacitors
R

4R

+15V

0.1uF

Vo(s)

TLO72C

Vi(s)

0.1uf

-15V

C

C

Example
• Find the circuit transfer function Vo(s)/Vi(s)
• Find the Frequency Response |Av(jw)| and /_Av(jw)
• Find the Filter Type and Design Equations for Fc or Fo and Q
• Start by assuming an ideal opamp is utilized
R

4R

+15V

0.1uF

Vo(s)

TLO72C

Vi(s)

0.1uf

-15V

C

C

Example

B

Analysis

A

• At Node B: (Vb = Vo)

(Va-Vo)/4R = VosC   Va = Vo(1 + 4sRC)

• At Node A:

(Vi-Va)/R = (Va-Vo)sC + (Va-Vo)/4R

Vo

Looks like a Lowpass Filter Transfer Function

At F = 0hz  Av = 1

At F = hz  Av = 0

8

Substitute and solve for Vo/Vi = Av(s)

Av(s) = 1 / {(2RC)s2 + (5RC)s + 1}

R

4R

+15V

0.1uF

Vo(s)

TLO72C

Vi(s)

0.1uf

-15V

C

C

Example

B

A

Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}

Av(jw) = 1 / {-(2RC)2w2 + (5RC)jw + 1}

| Av(jw)| = 1 / sqrt {Real2 + Imag2}

| Av(jw)| = 1 / sqrt { [1-(2RCw)2]2 + [5RCw]2 }

/_ Av(jw) = Tan-1(Num) - Tan-1(Den)

/_ Av(jw) = 0 - Tan-1(Imag/Real)

/_ Av(jw) = 0 - Tan-1{[5RCw]/ [1-(2RCw)2]}

Vo

Example: R = 10K, C = 0.01uF

F = 100Hz  |Av| = 1.0  |Av|dB = -0.28

F = 1Khz  |Av| = 0.31  |Av|dB = -10.09

F = 10Khz  |Av| = 0.006  |Av|dB = -44.08

F = 100Khz  |Av|dB = -88

2nd Order Lowpass Filter

R

4R

+15V

0.1uF

Vo(s)

TLO72C

Vi(s)

0.1uf

-15V

C

C

Example

B

A

Av(s) = 1 / {(2RC)2s2 + (5RC)s + 1}

Av(s) = 1/(2RC)2 / {s2 +(5/(2RC))s + (1/(2RC)2)}

In the 2nd order form of …

Av(s) = G wo2 /{s2 + (wo/Q)s + wo2}

wo2 = 1/(2RC)2 =  wo = 1/2RC  Fo = 1/(4pRC)

wo/Q = 5/(4RC)  (1/2RC)/Q = 5/(4RC)

 Q = 2/5 = 0.40

G wo2 = 1/(2RC)2  G = 1

Vo

Example: Design a 2nd order lowpass filter with Fo = ~800hz

Fo = 1/(4p(10k)(0.01uf))  795 hz

Let R = 10K, 4R = 40K, C = 0.01uf

Summary of Basic Biquadratic Filter Transfer Functions T(s):

Note: Many texts will define Fo as the –3dB frequency or corner frequency.

However, it is really just the “peak” of the transition band range of the filter as shown on the response curves. The actual value of Av (or T) depends on the damping factor Q of the filter.

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Classic Multi-Function Filter Design

Summing Inv Amp

Vout BP

Vin

-1

R1

C1

R2

C2

-1

+

A1

-1

Vout HP

A2

Vout LP

Rp

Rp

Inv Amp

-B

Filter Simulation of Component Tolerances
• Worst Case Analysis:
• Transfer Function Analysis
• Total DC Offset error in Volts
• Mag (dB) & Phase (deg) vs Frequency Plots
• Power Bandwidth for Application
• Pulse Response
Linear
• Oscillators
Oscillators
• Critical Factors:
• Passive Component Tolerances
• Output Slew Rate and Output Vp-p at Frequency of Oscillation
• Worst Case Analysis:
• Transfer Function Analysis of any Linear Feedback Circuit
• Forward path gain Analysis at 0 or 180 deg phase response
• Mag (dB) & Phase (deg) Margins vs Frequency Plots (1,2)
• Variation of Fo (1,2)
• Power Bandwidth (3)
Oscillators
• Oscillation Crition:
• The open loop gain (gain around the loop) must be exactly = 1.0
• The open loop phase (phase around the loop) must be exactly = 0o

Typically 2 types of amplifiers are utilized

Non-Inverting: Phase contribution = 0o = 360o

Inverting: Phase contribution = 180o

R / (1 + sCR)

R/(1 + sCR) + R + 1/sC

sCR

(sCR)2 + 3sCR + 1

(1 + R2/R1)(sCR)

(sCR)2 + 3sCR + 1

Wein Bridge Oscillator

RC Feedback Network Gain

R//(1/sC)

R//(1/sC) + R + 1/sC

R // (1/sC)  R / (1 + sCR)

Total Loop Gain Ab(s)

Total Loop Gain – Magnitude |Ab(jw)|

(1 + R2/R1)(wCR)

SQRT {[1 - (wCR)2]2 + [3wCR]2}

3wCR

1 - (wCR)2

3wCR

1 - (wCR)2

90o – TAN-1

270o – TAN-1

(1 + R2/R1)(sCR)

(sCR)2 + 3sCR + 1

(1 + R2/R1)(jwCR)

- (wCR)2 + 3jwCR + 1

Wein Bridge Oscillator

Total Loop Gain – Steady State Analysis

Total Loop – Phase /_Ab(jw)

Total Loop Phase /_Ab(jw) including inverting amplifier must be 0 to satisfy criterion #2

= 0o

3wCR

1 - (wCR)2

- TAN-1

Wein Bridge Oscillator

Total Loop Phase /_Ab(jw) including inverting amplifier must be 0 to satisfy criterion #2

= 90o

Can only occur, when;

1 - (wCR)2

= 0

w= 1/RC

Total Loop – Magnitude |Ab(jw)| @ w = 1/RC Must be = 1.0 to satisfy criterion #1

(1 + R2/R1)

SQRT {[3]2}

= 1.0 

(R2/R1) = 2.0

If R2/R1 = 2, oscillations occur

If R2/R1 < 2, oscillations attenuate

If R2/R1 > 2, oscillation amplify and then saturate

A = 3

A = 2.9

A = 3.05

Diodes D1 and D2 begin conducting when sufficient amplitude is reached at Vo

They effectively combine R4 in parallel with R3 for some of the voltage swing

Results of Diode Network
• With the use of diodes, the non-ideal op-amp can produce steady oscillations.
• Output waveform will show some distortion due to discontinuity caused from diode switching every cycle
Improved Automatic Gain Control
• P-Channel FET Q1 begins increasing Rds when sufficient amplitude is reached at Vo
• D1 is used to rectify and sample the output voltage
• R1, R2 and C1 are used to filter and store a scaled version of the sampled, rectified output voltage
• Rg + RQ1 (Rd ON) is set to = ~ RF / 2
• When the voltage on C1 increases as oscillations startup, RQ1 starts to increase which decreases the amplifier gain.
• The entire effect is completely linear so virtually no distortion is imposed on the output sine wave
Phase Shift Oscillator

Note A is Inverting

Bubba Oscillator (Modified Phase Shift)

Note A is Inverting

Comparators & Timers
• Definition 1: A class of circuits in which 2 analog voltages are compared and the output is a digital signal indicating > or <
• Definition 2: An integrated circuit which has a high gain differential amplifier input stage similar to an op-amp but an output stage which is only capable of driving a digital signal corresponding to the > or < condition of the inverting and non-inverting inputs
Comparators
• Critical Factors:
• Passive Component Tolerances, Diode Clamp Tolerances
• Input Offset Voltage (Vio)
• Input Bias Current (Ib), Input Offset Current (Iio)
• Voh, Vol clamping voltages
• Output Slew Rate and Delay
• Vref Tolerance
• Worst Case Analysis:
• Vutp and Vltp (upper and lower trip points, 1,2,3,4,6)
• Total hysteresis voltage (1-4,6)
• Max switching frequency (5)
--

+

Comparator Circuit

Vcc -Vcc

Rb

Vin

Vout

Non-linear opamp output

Vout = Vh or Vout = VL

Vh < Vcc, VL > -Vcc

Vh and VL values typically 0.5 to 3V below Vcc

V+ = {(Vout – Vref) (Ri) / (Ri + Rf)} + Vref, V- = Vin

Assume Vo = Vh and V+ >V- but Vi is increasing

If Vi > (Vout – Vref) (Ri) / (Ri + Rf) + Vref, Vo  VL

The upper trip point (Vutp) is found as;

Vutp = {(Vh – Vref) (Ri) / (Ri + Rf)} + Vref

Rf

Ri

Positive Feedback

Hysteresis Resistor

Vref

When V+ > V-, then Vo = Vh

When V+ < V-, then Vo = VL

Vin is compared against Vref

--

+

Comparator Circuit

Vcc -Vcc

Rb

Vin

Vout

Non-linear opamp output

Vout = Vh or Vout = VL

Assume now Vo = VL and V+

If Vi < (VL – Vref) (Ri) / (Ri + Rf) + Vref, Vo  Vh

The lower trip point (Vltp) is found as;

Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} + Vref

Rf

Ri

Positive Feedback

Hysteresis Resistor

Vref

When V+ > V-, then Vo = Vh

When V+ < V-, then Vo = VL

Vin is compared against Vref

--

+

Comparator Circuit Example

+Vcc -Vcc

Rb

Vin

Vout

Vltp = {(VL – Vref)(Ri) / (Ri + Rf)} + Vref

Vutp = {(Vh – Vref)(Ri) / (Ri + Rf)} + Vref

Rf

Vh

Ri

Vref

Vref

Vltp

Vutp

The rectangular shape is known as a

Hysteresis Diagram

Vl

--

+

Comparator Circuit Example

+15V -15V

10K

Vin

Vout

Vltp = {(-13 – 5) (10k) / (10k + 100k)} + 5

Vltp = 3.36V

Vutp = {(13 – 5) (10k) / (10k + 100k)} + 5

Vutp = 5.73V

100K

Vh = ~13V

VL = ~-13V

13v

10K

5v

Vref = 5V

3.36v

5.73v

Vhyst = Vutp – Vltp = 2.37V

-13v

--

+

Controlling Vh and VL voltages

Vcc -Vcc

Rb

RL

Vin

Vh or VL

Must have current limiting

Resistor RL when using a

Voltage Clamp

(Vh-Vout)/RL < Imax for opamp

Imax (typical) = ~ 5mA

Vout

Rf

Voltage

Clamp

Ri

Positive Feedback

Hysteresis Resistor

Vref

Controlling Vh and VL give greater utility for Comparator

Controlling Vh and VL voltages

RL

Diode String Clamp

Vh = Vd1+Vd2+Vd3 = ~2.1v

VL = -Vd4-Vd5 = ~-1.4v

D1

D4

D1

Vout

D4

Z1

Z1

D2

Voltage

Clamp

D5

D2

Z2

D3

D3

Stacked Zener Clamp

Vh = Vd1+Vz2

VL = -Vz1-Vd2

Zener Bridge Clamp

Vh = Vd1+Vd2+Vz1

VL = -Vd3-Vd4-Vz1

Vh = -VL

Types of Voltage Clamps

--

+

Controlling Vh and VL voltages

Vcc -Vcc

Rb

RL

Vin

Vh or VL

Vout

Rf

Vh

Voltage

Clamp

Ri

Positive Feedback

Hysteresis Resistor

Vref

Vref

Vutp

Vltp

NOTE: If Vh < Vref, Vref may be outside of Vltp-Vutp window

But hysteresis will still work

Vl

--

+

Schmitt Trigger - Comparator

Vcc -Vcc

Rb

Vin

Vout

Vltp = (VL) (Ri) / (Ri + Rf)

Vutp = (Vh) (Ri) / (Ri + Rf)

Rf

Ri

Vref = 0

In a Schmitt Trigger, Vref = 0V

--

+

C

Comparator – RC Oscillator

R2

D2

D1

R1

Vcc -Vcc

Rb

Vin

RL

Vout

Rf

Voltage

Clamp

Ri

Vref = 0

Schmitt Trigger used in a Relaxation Oscillator

R2

D2

D1

R1

Vcc -Vcc

Rb

Vin

RL

Vout

-

+

C

Rf

Voltage

Clamp

Ri

Vref = 0

Comparator – RC Oscillator

Th = -(R1C) ln{(Vutp-Vh-Vd1)/(Vltp-Vh+Vd1)}

TL = -(R2C) ln{(Vltp-VL-Vd2)/(Vutp-VL+Vd2)}

Note:

For Ri = Rf = Rb, R1//R2 = R, No Diodes & Vh = -VL

Vutp = -Vltp = 1/2Vh

Th = -(RC) ln {(Vutp-Vh)/(Vltp-Vh)} = -RC ln (1/3)

TL = - RC ln (1/3)

F = -1 / {2RC ln (1/3)} = 0.455/RC

Individual High and Low Times can be set with Th & TL

R2

D2

D1

R1

Vcc -Vcc

Rb

Vin

RL

Vout

-

+

C

Rf

Voltage

Clamp

Ri

Vref = 0

Comparator – RC Oscillator

Vh

Th

Vutp

0

Vltp

TL

VL

Capactor Voltage & Output Waveforms

Voltage Regulators, Power Supplies
• Critical Factors:
• Passive Component Tolerances (voltage set resistors)
• Input voltage DC, AC and noise levels
• Filtration Capacitors
• Ambient Temperature
• Worst Case Analysis:
• DC Output voltage variation (1,2,3)
• AC Output ripple, noise (2,3,4)
• Critical device power dissipation, Junction Temp (2,3,5)
• Startup Output voltage vs Input voltage vs Time (2,3,4)
• Safety Considerations
Typical Linear Regulator Circuit

Pass Transistors May be Reconfigured for LDO or Low Dropout Performance

Note: Power Dissipated = (Vin-Vout)Iin

Typical Thermal Shutdown Protection System

Pass Transistor is Forced Off in Thermal Shutdown

Most low cost regulators do NOT latch this condition

Basic Buck Switching Regulation Sys

Vin > Vout

Basic Boost Switching Regulation Sys

Vin < Vout

Buck-Boost Inverting Switching Regulation System Architecture

Coasting Diode Conducts Inductor Current during the Switch Off Cycle which pulls current from Load creating a negative polarity on the Capacitor

Coasting Diode is reverse biased during the Switch On Cycle. Capacitor C continues load current direction due to negative charge

Capacitor Equiv Circuit

With Parasitics Modeled

DATA ACQUISITION

Basics of Converter Technology

• Function
• Data Sheet Characterizations
• Quantization Error and SNR
• Gain, Offset Errors
• Linearity Errors and THD
DATA ACQUISITIONBASICS

ANALOG VOLTAGE RANGE

VFS

QUANTIZED INTO

2n LEVELS

WHERE n = # OF BITS

Nominal Quantization Step

0 1 2 3 4 5 6 7 8 9 10 11

Nominal Step Size Q = VFS/2n

Highest Voltage Step = VFS – Q

Max Count = 2n–1 (0 is a valid step)

Quantization Error

Note: Last step occurs at VFS(N-1)/N under ideal conditions

Voltage is Measured as Fraction of a reference Vref

VFS = Vref

Quantization Error

Ideal 3 Bit A/D Converter Transfer Function

n

D/A

A/D

• Max Quantization Error:
• Qerr = VFS/(2n) = 1 bit
SNR = 20 log(2(n-1) * sqrt(6) )

= 20log (2(n-1)) + 20log (sqrt(6))

= 20(n-1)log(2) + 20log (sqrt(6))

= 20nlog(2)-20log(2)+20log (sqrt(6))

= 20nlog(2) + 20log (sqrt(6)/2)

= 6.02n + 1.76

n

D/A

A/D

Sinewave MAX SNRDB = 6.02n + 1.76

• Max Quantization Error, Qerr = VFS/(2n) = 1 bit
• More Resolution (higher n) means less quantization error
• Examples:
• VFS = 10V, n = 8 Bit, Qerr = 39.96mV, SNRmax = 49.9DB
• VFS = 10V, n = 12Bit, Qerr = 2.44mV, SNRmax = 74.0DB
• VFS = 10V, n = 16Bit, Qerr = 0.16mV, SNRmax = 98.1DB
• More Resolution may require, slower speed, higher power
Converter Offset Error
• Example of ½ Bit Offset Error
• Offset Error: Shifts Ideal Staircase Function Right (+) or Left (-) by Max Voltage or Max LSBs
Converter Gain Error
• Gain Error will change the converter “slope”
• Gain Error: Changes Ideal Staircase Function so that last step is not at VFS(N-1)/N
Integral Linearity Error: Max Deviation from Ideal Straight Line

(INL: Integral Non-Linearity)

Xfer Curve drawn at midpoint of each input step (ideal vs actual)

(DNL: Differential Non-Linearity)

DNL max > 1 Bit can lead to missing codes

• ENOB: Effective Number of Bits
• Combination of SNR and THD specifications
• Measure of overall “usable” Dynamic Performance

In Ideal Converter ENOB = n

Power Supplies are Extremely Important !!
• PSRR: Power Supply Rejection Ratio
• Measure of output noise injected by PS noise
• PSRR is function of frequency
• A/D converters require “quiet” supply voltages
• Isolate supply voltages using separate regulators
A/D Converter Architectures
• Flash High Speed, High Power
• Integrating High Resolution, Parallel
• Successive Approximating Low Resolution, High Speed
• Delta-Sigma High Resolution, Low Cost
Successive Approximating (SAR)

END OF CONV

SUCCESSIVE

APPROXIMATION

REGISTER

n-1

n-2

n-3

Decision signal

n

OUTPUT

BITS

CONTROL

CLOCK

Clock

n-n

V Ref

n-1

B

BIT

D/A

Converter

COMPARATOR

n-2

n-3

Buffer

V in

n-n

Integrating

COUNTER

n-1

n-2

n Output Bits

n-3

Buffer

V in

n-n

CLOCK

Clk

COMPARATOR

Clr

Current

Source

CONTROL

I

C

FLASH

V Ref

OUTPUT

LOGIC

REGISTER

n-1

n-2

n-1

n Output Bits

n-2

BUFFER

V in

n-3

n-n

2n –1 COMPARATORS

1

Classic 555 Timing IC – Not Recommended for New Designs

In early bipolar versions, R = 5K, hence the “555” name

555 Timing IC

Pulse Generator Application of Typical 555 Timer IC

555 Timing IC

Relaxation Oscillator Application of Typical 555 Timer IC