Memory Interfacing

1. Memory Interfacing ECE 511: Digital System & Microprocessor

2. What we will learn in this session: • Review several important aspects of memory access. • Buffering and its importance in a M68k system. • Types of memory. • How to design a Memory Address Decoder: • Full addressing • Partial addressing

3. M68k & Memory • M68k has limited space to store data & instructions: • 8 x Data registers. • 1 x Instruction Register. • Not enough for practical applications. • Memory expands storage space: • Stores instructions & data in memory.

4. M68k & Memory • M68k has 24-bit (23 + 1) address bus: • Can address 224 locations. • 16,777,216 locations (16 MB). • Can store much more data, instructions.

5. Bus Buffering

6. Bus Buffering • The system bus consists of: • Address bus: A1 – A23 • Data bus: D0 – D15 • Control bus: BERR, VPA, CLK, R/W, etc..

7. Bus Buffering • System bus is connected to all components in µP system: • Memory: RAM, ROM. • I/O devices: keyboard, mouse, display card. • Storage devices: HDD, CD-ROM drive.

8. Block Diagram Parallel I/O Serial I/O Interrupt Circuit System Bus = Data Bus + Address Bus + Control Bus Timing CPU Memory

9. Fan-Out • All connected devices drain current from M68k. • If too many devices connected, M68k fan-out overloaded: • Causes unreliable input/output. • Fan-out specified by manufacturer.

10. -0.8 mA -0.8 mA -0.8 mA -0.8 mA Fan-Out: Normal Situation Device #1 Device #2 Device #3 Device #4 Address Bus (M68k fan-out limit = 3.2mA)

11. -0.8 mA -0.8 mA -0.8 mA -0.8 mA -0.8 mA -0.8 mA Fan-Out: Overloaded Situation Device #1 Device #2 Device #3 Device #4 Device #5 Device #6 Address Bus (M68k fan-out limit = 3.2mA)

12. Bus Buffering • Increases M68k fan-out limit by attaching high-current buffer to system bus. • Can connect more devices. • Common buffers: • 74LS244 unidirectional buffer: can transfer data in one direction only. • 74LS245 bidirectional buffer: can transfer data in both directions. • Each IC can buffer 8 lines only.

13. A1 – A8 (FOL = 3.2mA) 74LS244 A1 – A8 (FOL = 24mA) M68k To devices A9 – A16 (FOL = 3.2mA) 74LS244 A9 – A16 (FOL = 24mA) To devices A10 – A23 (FOL = 3.2mA) 74LS244 A10 – A23 (FOL = 24mA) To devices Address Bus Buffering

14. 74LS245 D0-D8 (FOL = 3.2mA) D0-D8 (FOL = 24mA) To devices M68k DIR If R/W = 1, direction into M68k, If R/W = 0, direction to devices. R/W 74LS245 DIR D9-D16 (FOL = 3.2mA) D9-D16 (FOL = 24mA) To devices Data Bus Buffering

15. Buffering in M68k System Parallel I/O Serial I/O Interrupt Circuit System Bus = Data Bus + Address Bus + Control Bus 74LS244 74LS245 Timing CPU Memory

16. Bus Buffering • All pins in M68k need to be buffered: • Address bus: buffered using 74LS244. • Data bus: buffered using 74LS245. • Control bus: buffered using 74LS244/74LS245: • If unidirectional, use 74LS244. • If bidirectional, use 74LS245.

17. +5V VCC VCC Data Bus D0-D15 CLK Address Bus A1-A23 AS FC0 R/W Asynchronous Bus Control Processor Status FC1 UDS 68000 FC2 LDS DTACK E 6800 Peripheral Control VMA BR Bus Arbitration Control VPA BG BERR BGACK System Control RESET IPL0 Interrupt Control HALT IPL1 GND GND IPL2 M68k Pin-Out *A0 is used inside 68k

18. Designing with Available Memories

19. Types of Memory • Typically, M68k systems are designed with 2 types of memory: • EPROM: Erasable Programmable Read-Only Memory. • SRAM: Static Random Access Memory. • To design a memory system, it’s important to know the name and size of chip.

20. Typical EPROM Chips Part Size Address Lines 2716 2kB 11 2732 4kB 12 2764 8kB 13 27128 16kB 14 27256 32kB 15 27512 64kB 16

21. Typical SRAM Chips Part Size Address Lines 6116 2kB 11 6264 8kB 13 62256 32kB 15

22. Typical EPROM Chips 2716 EPROM 27512 EPROM

23. Typical SRAM Chips 2716 EPROM 62256 SRAM

24. Characteristics • ROM chips have OE* (output enable) and CS* (chip select). • RAM chips have E* (enable), CS* (chip select), and WE* (write enable). • To activate a RAM/ROM chip, both OE*/E* and CS* must be active.

25. Characteristics • OE*/E* is connected to UDS*/LDS*. • CS* is connected to Memory Address Decoder. • WE* is connected to R/W* pin on M68k. • If R/W* = 1, read from memory. • If R/W* = 0, write to memory.

26. AS OE OE WE WE CS CS R/W *Chip activated only when OE and CS are active. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 Address Bus D1 D2 UDS D3 D4 D5 D6 Memory Address Decoder D7 Chip #2 D0 D1 D2 D3 R/W D4 LDS D5 D6 D7 Chip #1

27. Memory Decoding

28. Memory Decoding • Method to access data in memory. • Enables/disables certain chips based on data required. • Done using special circuit – Memory Address Decoder (MAD).

29. Memory Address Decoder (MAD) • Special circuit. • Connected to address bus. • Activates specific memory chips based on address pattern in address bus. • 2 methods to design: • Full address decoding (FAD) • Partial address decoding (PAD)

30. UDS LDS OE OE WE WE CS CS R/W R/W *Chip activated only when OE and CS are active. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 Address Bus D1 D2 D3 D4 D5 D6 Memory Address Decoder D7 Chip #2 D0 D1 AS D2 D3 D4 D5 D6 D7 Chip #1

31. Full Address Decoding • Uses all available address lines to design decoder: • All 23 lines used for addressing/decoding. • Since all lines used, decoder circuit design is more complex. • Used in systems with large memory.

32. Partial Address Decoding • Uses only uses a few address lines to design decoder: • Some lines are not connected to decoder circuit. • Typically used in systems with smaller memory. • Decoder circuit design is simple, but hard to expand if more memory needs to be added later.

33. CS CS LDS UDS SEL Full Address Decoding Example ODD EVEN 512kB RAM 512kB RAM A1 – A19 A1 – A19 D0 – D7 D8 – D15 E E A23 A22 MAD A21 A20 AS *All address lines used – A1  A23 A20  A23 for MAD A1  A19 for addressing

34. AS CS CS CS CS LDS LDS UDS UDS E E Partial Address Decoding Example 2kB ROM 2kB ROM A1 – A11 A1 – A11 D8 – D15 D0 – D7 OE OE A12 SELROM MAD SELRAM 2kB RAM 2kB RAM A1 – A11 A1 – A11 D8 – D15 D0 – D7 *Not all address lines used: A12 for MAD A1  A11 for addressing

35. Comparison between FAD and PAD Full Address Decoder Partial Address Decoder Address lines used Uses all lines for addressing or decoding. Uses only a part of address lines for addressing or decoding. The rest ignored. MAD circuit More complex circuit, since need to use all address lines. Less complex circuit, since only a few address lines are used. When to use When the M68k system is large and requires a lot of memory. When M68k system has small memory requirements. Upgrade Easy to upgrade, extra memory can be added with little modifications to original decoder. Difficult to upgrade, requires complete redesign of decoder.

36. Full Address Decoder Design

37. Full Address Decoder Design • Determine available information. • Determine the required number of address lines. • Set base address. • Determine lower address range. • Determine upper address range. • Design decoder. • Draw memory block diagram.

38. Example #1

39. Example #1 • 512kWords (1024 kB) of RAM needs to be interfaced to a 68k-based system, The base address is $400000. Design the decoder circuit.

40. Step 1: Determine Available Information • Three things must be determined: • How much memory to interface. • Base address of memory. • How many chips need to be used.

41. Step 1: Determine Available Information • 1024 kB need to be interfaced: • RAM needs to be interfaced. • 2 chips used. • 512kB for even address (UDS), 512kB for odd address (LDS). • Base address is $400000.

42. Step 1: Determine Available Information 1024 kB (512 kWords) Chip #1 (512 kB) (even addresses) Chip #2 (512 kB) (odd addresses) * Controlled by LDS * Controlled by UDS

43. Step 2: Determine Number of Required Address Lines • Determines how many address lines need to be used by one chip. • Use the following formula: y = storage size of one chip (kB) x = number of reserved lines

44. Step 2: Determine Number of Required Address Lines • Each chip contains 512,000 memory locations: • Needs 19 address lines. *Always round to higher.

45. Step 3: Allocate Address Line • Address lines allocated based on Step 2. • Start with A1. • Fill with don’t cares (X).

46. UDS/LDS (reserved) Step 3: Allocate Address Line A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X X X X X X X X X X X X X X X X X X X 19 lines allocated

47. Step 4: Set Base Address • Set base address using the remaining address lines.

48. UDS/LDS (reserved) Step 4: Set Base Address A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 X X X X X X X X X X X X X X X X X X X 4 * Base address is $400000

49. Step 5: Determine Lower Address Range • Replace all don’t cares and A0 with zeros. • Should get the same base address as question.

50. Step 5: Determine Lower Address Range A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 Fill with zeros A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 Lower range: $400000