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Memory & IO Interfacing to CPU

Memory & IO Interfacing to CPU. Lec note 3. outline. Z80 Minimal Configuration Z80 Memory connection Address Bit Map Memory Map Full and Partial Decoding 1 Bit Memory With Separated I/O Z80 Input Output Simplified Drawing of 8088 Minimum Mode 8088 Memory connection.

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Memory & IO Interfacing to CPU

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  1. Memory & IO Interfacing to CPU Lec note 3

  2. outline • Z80 Minimal Configuration • Z80 Memory connection • Address Bit Map • Memory Map • Full and Partial Decoding • 1 Bit Memory With Separated I/O • Z80 Input Output • Simplified Drawing of 8088 Minimum Mode • 8088 Memory connection

  3. Minimal Configuration of a Z80 Microcomputer

  4. Z80 Memory connection • CPU 16 bit address bus  64 k memory(max) • CPU 8 bit data bus  8 bit data width • Generally should be connected • Data to data • Address to address • Wr to wr • Rd to rd • Mreq to cs

  5. D7~D0 D7~D0 RAM 64 kb A15~A0 A15~A0 Z80 CPU Memory connection (cont.) • If only one RAM chip Full size (64 kb capacity)

  6. D7~D0 D7~D0 RAM 32 kb A14~A0 A14~A0 Z80 CPU A15 Memory connection (cont.) • If RAM capacity was 32 kb • A15 composed with MREQ • RAM area is from 0000h to 7FFFh

  7. Memory connection (cont.) • There is two 32 kb RAM • Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. • Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.

  8. D7~D0 D7~D0 D7~D0 RAM 32 kb RAM 32 kb A14~A0 A14~A0 A14~A0 Z80 CPU A15 Memory connection (cont.) • There is two 32 kb RAM • A15 applied to select one RAM chip • TwoRAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh(RAM1)

  9. D7~D0 D7~D0 D7~D0 ROM 32 kb RAM 32 kb A14~A0 A14~A0 A14~A0 Z80 CPU A15 Memory connection (cont.) • 32 kb ROM and 32 kb RAM • ROM doesn’t have wr signal

  10. D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 ROM 16 kb RAM 16 kb RAM 16 kb RAM 16 kb A13~A0 A13~A0 A13~A0 A13~A0 A13~A0 En A15 A14 S0 S1 Memory connection (cont.) There is 4 memory chip A14 and A15 applied to chip selection Z80 CPU

  11. Address Bit Map Selects chip Selects location within chips

  12. D7~D0 D7~D0 D7~D0 D7~D0 D7~D0 ROM 16 kb RAM 16 kb RAM 16 kb RAM 16 kb A13~A0 A13~A0 A13~A0 A13~A0 A13~A0 En A15 A14 S0 S1 Memory Map • Represents the memory type • Address area of each memory chip • Empty area

  13. D7~D0 D7~D0 D7~D0 D7~D0 ROM 16 kb RAM 16 kb RAM 16 kb A13~A0 A13~A0 A13~A0 A13~A0 En A15 A14 S0 S1 Memory Map • Empty Area cann’t write and read • Read op. returns FFh value (usualy) • Write op. cann’t store any value on it

  14. D7~D0 D7~D0 D7~D0 ROM 16 kb RAM 16 kb A13~A0 A13~A0 A13~A0 En A15 A14 S0 S1 Memory Map • Empty Area cann’t write and read • Read op. returns FFh value (usualy) • Write op. cann’t store any value on it

  15. Full and Partial Decoding • Full (exhaust) Decoding • All of the address lines are connected to any memory/device to perform selection • Absolute address : any memory location has one address • Partial Decoding • When some of the address lines are connected the memory/device to perform selection • Using this type of decoding results into roll-over addresses (fold back or shading). • roll-over address : any memory location has more than one address

  16. D7~D0 D7~D0 RAM 4 kb A11~A0 A11~A0 A15~A12 X Z80 CPU Partial Decoding • A15~A12 has no connection • Then doesn’t play any role in addressing • What is the Memory and Address Bit map?

  17. D7~D0 D7~D0 RAM 4 kb A11~A0 A11~A0 A15~A12 X Z80 CPU Partial Decoding • Every memory location has more than one address • For example first RAM location has addresses: • 0000h • 1000h • 2000h • 3000h ……………. ……………. • F000h Roll-over Address

  18. Partial Decoding • A12 only connected to RAM • A13 has no connection • What is the memory map? D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A12~A0 A11~A0 A12~A0 X A13 Z80 CPU A15 A14

  19. D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A11~A0 A12~A0 A12~A0 Z80 CPU X A13 A15 A14 Partial Decoding • 8 roll-over address for ROM • 4 roll-over address for RAM

  20. D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A11~A0 A12~A0 A12~A0 Z80 CPU X A13 A15 A14 Partial Decoding Conflict

  21. D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A11~A0 A12~A0 A12~A0 Z80 CPU X A13 A15 A14 Partial Decoding Conflict

  22. C Y0 B Y1 A Y2 Y3 74138 Y4 Y5 G2A Y6 G2B G1 Y7 Full (exhaustive) decoding A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 A13 0000h-07FFh A12 0800h-0FFFh 7421 A11 1000h-17FFh A10~A0 A10~A0 1800h-1FFFh D7~D0 6116 RWM 2k8 2000h-27FFh A15 A14

  23. C Y0 B Y1 A Y2 Y3 74138 Y4 Y5 G2A Y6 G2B G1 Y7 Partial decoding A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 A15 0000h-1FFFh A14 2000h-3FFFh A13 A10~A0 A10~A0 D7~D0 6116 RWM 2k8 GND VCC

  24. 1 Bit Memory With Separated I/O D7-D0 D7 D1 D0 Din Din Din A11~A0 A11~A0 A11~A0 Dout Dout Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1

  25. C Y0 B Y1 A Y2 Y3 74138 Y4 Y5 G2A Y6 G2B G1 Y7 What is the memory(addr. bit) map A12~A0 D7~D0 2764 EPROM 8k8 A15 0000h-1FFFh 2000h-3FFFh A14 D7-D0 D0 D7 D1 A13 Din Din Din A11~A0 A11~A0 A11~A0 Dout Dout Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1 GND VCC

  26. Adding RAM & ROM

  27. Minimum Z80 Computer System

  28. Z80-µP-Family (Typical Environment)

  29. Z80 Input Output • Z80 at most could have 256 input port and 256 output • 8 bit port address is placed on A7–A0 pin to select the I/O device • OUT (n), A • n is 8 bit port address • Content of A is data • OUT (C), r • Content of C is a port address • r is a data register • IN A, (n) • n is 8 bit port address • Data is transfered to A • IN r (C) • Content of Reg C is a port address • Input data is transfered to r (data reg)

  30. Remember IO read/write cycle

  31. A15 A14 : A0 D0 Q0 D7 D1 Q1 D6 D2 Q2 D5 Z80 CPU D3 Q3 D4 D4 Q4 D3 74LS373 D5 Q5 D2 D6 Q6 D1 D7 Q7 D0 LE OE IORQ WR A A A A A A A A 7 6 5 4 3 2 1 0 IOWR Z80 and simple output port OUT (03), A

  32. Z80 and simple input port IN A, (02) 5V A15 A14 : A0 Y0 A0 D7 Y1 A1 D6 Y2 A2 D5 Z80 CPU Y3 A3 D4 Y4 A4 D3 74LS244 Y5 A5 D2 Y6 A6 D1 Y7 A7 D0 G1 G2 IORQ RD A A A A A A A A 7 6 5 4 3 2 1 0 IORD

  33. A19 A18 : A0 D0 Q0 D7 D1 Q1 D6 D2 Q2 D5 D3 Q3 D4 D4 Q4 D3 74LS373 D5 Q5 D2 8088 D6 Q6 D1 Minimum D7 Q7 D0 Mode LE OE IOR IOW A A A A A A A A A A A A A A A A IOW 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 8088 and simple output port

  34. 5V A19 A18 : What is this? A0 Y0 A0 D7 Y1 A1 D6 Y2 A2 D5 Y3 A3 D4 Y4 A4 D3 74LS244 Y5 A5 D2 8088 Y6 A6 D1 Minimum Y7 A7 D0 Mode G1 G2 IOR IOW A A A A A A A A A A A A A A A A IOW 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 8088 and simple input port

  35. D7-D0 A7 - A0 B7 - B0 DEN E 74LS245 DT/R DIR A7-A0 D7 - D0 Q7 - Q0 AD7 - AD0 GND OE 74LS373 LE A15-A8 A15 - A8 D7 - D0 Q7 - Q0 GND OE 8088 74LS373 LE A19-A16 Q7 - Q4 D7 - D4 A19/S6-A16/S3 D3 - D0 Q3 - Q0 GND OE 74LS373 ALE LE MEMR RD IO / M MEMW WR IOR IOW Simplified Drawing of 8088 Minimum Mode

  36. D7 - D0 D7 - D0 A19 - A0 A19 - A0 Simplified Drawing of 1 MB Memory 8088 Minimum Mode MEMR RD MEMW WR CS Minimum Mode 220 bytes or 1MB memory

  37. Memory location What is the memory location of a 1MB (220 bytes) Memory? Example: 34FD0 0011 0100 11111 1101 0000

  38. Minimum Mode 512 kB memory D7 - D0 D7 - D0 • What do we do with A19? • Don’t connect it • Connect to cs • What is the difference? A19 A18 - A0 A18 - A0 Simplified Drawing of 512 kB Memory 8088 Minimum Mode MEMR RD MEMW WR CS

  39. 512 kB Memory Map • Don’t connect it • A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it. • A19=0 is the same as A19=1 for Memory • Connect to cs • If A19=0 Memory chip act normal fanction

  40. 2  512 kB memory D7 - D0 D7 - D0 512 kB RAM1 A19 A18 - A0 A18 - A0 RD MEMR WR CS MEMW Simplified Drawing of 8088 Minimum D7 - D0 Mode 512 kB RAM2 A18 - A0 RD MEMR WR CS MEMW

  41. 2512 kB memory What are the memory locations of two consecutive 512KB (219 bytes) Memory?

  42. A17 : A0 D7 256KB : #4 D0 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : #3 D0 D0 MEMR RD MEMW WR 8088 CS Minimum A17 Mode : A0 D7 256KB : #2 D0 RD WR CS A17 : A0 D7 256KB : #1 D0 RD WR CS Interfacing four 256K Memory Chips to 8088 Microprocessor

  43. A17 : A0 D7 256KB : #4 D0 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : #3 D0 D0 MEMR RD MEMW WR 8088 CS Minimum A17 Mode : A0 D7 256KB : #2 D0 RD WR CS A17 : A0 D7 256KB : #1 D0 RD WR CS Interfacing four 256K Memory Chips to 8088 Microprocessor

  44. Memory chip#__ is mapped to:

  45. A12 : A0 D7 A19 8KB A18 : #? D0 A17 RD A16 WR A15 A14 CS A13 A12 : : A0 D7 : : D0 MEMR MEMW 8088 Minimum Mode A12 : A0 D7 8KB : #2 D0 RD WR CS A12 : A0 D7 8KB : #1 D0 RD WR CS Interfacing several 8K Memory Chips to 8088 P

  46. A12 : A0 A19 D7 8KB A18 : #128 A17 D0 A16 RD A15 WR A14 CS A13 A12 : : A0 D7 : : D0 MEMR MEMW 8088 Minimum Mode A12 : A0 D7 8KB : #2 D0 RD WR CS A12 : A0 D7 8KB : #1 D0 RD WR CS Interfacing 1288K Memory Chips to 8088 P

  47. A12 : A0 A19 D7 8KB A18 : #128 A17 D0 A16 RD A15 WR A14 CS A13 A12 : : A0 D7 : : D0 MEMR MEMW 8088 Minimum Mode A12 : A0 D7 8KB : #2 D0 RD WR CS A12 : A0 D7 8KB : #1 D0 RD WR CS Interfacing 1288K Memory Chips to 8088 P

  48. Memory chip#__ is mapped to:

  49. C Y0 B Y1 A Y2 Y3 74138 Y4 Y5 G2A Y6 G2B G1 Y7 Memory map & Address Bit map A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 7408 A14 A13 A12 A10~A0 A10~A0 D7~D0 74244 input 6116 RWM 2k8 A15 VCC

  50. 8255 • Programmable Peripheral Interface (PPI) • Has 3 8_bit ports A, B and C • Port C can be used as two 4 bit ports CL and Ch • Two address lines A0, A1 and a Chip select CS • 8255 can be configured by writing a control-word in CR register

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