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Outline of the lecture : Chandana :

Introduction to Interrupts. Outline of the lecture : Chandana : 1. Introduction 2. Example 3. Definition 4. Vector table and Maskable / nonmaskable interrupts ________________________________________________ Hao : 5. Stack status 6. HPRIO 7. Example . Polling and Interrupts.

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Outline of the lecture : Chandana :

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  1. Introduction to Interrupts Outline of the lecture: Chandana: 1. Introduction2. Example 3. Definition 4. Vector table and Maskable/nonmaskable interrupts ________________________________________________ Hao: 5. Stack status 6. HPRIO 7. Example

  2. Polling and Interrupts • Polling- Imagine a phone without a bell. You would have to periodically answer the phone to see if anyone is there • Interrupt – Phone with a bell. You can do something else and stop and answer the phone when it rings

  3. Polling Pros and Cons Pros • Simple Implementation • Good for single I/O cases • Doesn’t need extra hardware Cons • Inefficient for complex systems • May not be fast enough for requirements

  4. Interrupts Pros vs. Cons Pros • Efficient for complex systems (great multitasking) • Can be ignored (masked) • Can be prioritized Cons • Tradeoff of hardware complexity • Can make debugging difficult due to unanticipated random occurrences

  5. Applications • Computer Keyboard • Stability Control System on Car • House security system • Pause button on television

  6. Ways Interrupts can be generated Hardware Interrupts • Peripherals such as a printer or fax machine • Computer Operator via keyboard, mouse or power on reset button • Another computer Software Interrupts • Timer resets • Timer interrupts • Traps • Request for input or output • Arithmetic overflow error

  7. Some Definitions • Interrupt Service Routine (interrupt handler): This is a “more important” instruction code that interrupts your main program code. The routine is specific to the type of interrupt called. • Interrupt Vector: This is an address in memory where the ISR instruction code is located. It is the starting address of the code. (Like a pointer) • Interrupt Vector Table: This is a table indicating the interrupt vector Main Program Blah blah blah Blah blah blah Blah blah blah Blah blah blah ISR Code Blah blah blah Blah blah blah Blah blah blah Blah blah blah RTI $FFF6

  8. Interrupt Flow A B Interrupt condition is met Analyze Priority ISR instruction YES Mask(s) set? Set (I) or (X) to prohibit another Interrupt RTI NO NO YES Complete Current Instruction Clear I or X bit in CCR Standard Interrupt Table Restore Registers w/ org. Values Store all registers on the Stack Load Address in appropriate vector Continue Program A B

  9. Non-Maskable Interrupts • 6 Non-MaskableInterrupts • Higher Priority than maskableinterrupts • Can interrupt Maskable Interrupt ISRs • X=1 ONLY disables XIRQ interrupt (and all other interrupts are still enabled when X=1) • POR of RESET pin • Clock monitor reset • COP watchdog reset • Unimplemented instruction trap • Software interrupt (SWI) • XIRQ interrupt

  10. XIRQ & IRQ

  11. Non-Maskable Interrupts • At Reset or during Non-Maskable interrupt • X=1 and I=1 • Interrupts cannot be serviced • Clear X bit • TAP instruction • ANDCC #$40 instruction • Software cannot set X bit once cleared unless non-maskable interrupt occurs • RTI restores X and I bits to pre-interrupt state

  12. Non-Maskable Interrupts • XIRQ • Externally triggered • PE0 pin low = XIRQ interrupt • SWI • Allows an interrupt without an event • MON12 in use: jumps back to DBug12 • Unimplemented Instruction Trap • CPU is given code with invalid opcode • Generates interrupt request to unimplemented instruction trap vector

  13. Maskable Interrupts • 27 Maskable Interrupts • Global Masking: controls execution of all maskable interrupts (ie. I bit =1, no maskable interrupts occur) • Local Masking: controls execution of interrupt on a peripheral device (ie. ATD) • IRQ • Real-Time Interrupt • Standard Timer Channel 0 • Standard Timer Channel 1 • Standard Timer Channel 2 • Standard Timer Channel 3 • Standard Timer Channel 4 • Standard Timer Channel 5 • Standard Timer Channel 6 • Standard Timer Channel 7 • Standard Timer Overflow • Pulse Accumulator A Overflow • Pulse Accumulator Input Edge • SPI transfer Complete • SCI system • ATD • Port J • CRG PLL Lock • CRG Self Clock Mode • Flash • CAN Wakeup • CAN Errors • CAN Receive • CAN Transmit • Port P • PWM Emergency Shutdown • VREG LVI

  14. Maskable Interrupts • IRQ • Only external maskable interrupt signal • IRQE bit on IRQCR Register • IRQE=1: High level-Sensitive • IRQE=0: Low Level-Sensitive • Peripheral Subsystems (all other Maskable Interrupts) • Flag bit and interrupt enable bit • ATD, Timers, PWM, serial communications, etc.

  15. Interrupt Vector Tables

  16. Interrupt Vector in Mon12 MON12 interrupt vectors are used. ($0F00-$0FFF ) • MON12’s calls ISR’s specified by the user in the $0Fxx range • The microcontroller calls ISR’s specified in the $FFxx range.

  17. Interrupts: Stack Higher Address Stack Pointer before Interrupt RTN LO First Pushed In Last Pulled Off RTN HI Y LO • RTN – address of next instruction in Main Program, upon return from interrupt. • X LO and Y LO are the low bytes of X and Y registers. • X HI and Y HI are the high bytes of X and Y registers. • ACC A and ACC B are the accumulators. • CCR is the Code Condition Register Y HI X LO X HI ACC A Last Pushed In First Pulled Off ACC B Stack Pointer after Interrupt CCR Lower Address

  18. Highest Priority Interrupt (HPRIO) Register Address: $001F • HPRIO register moves one maskable interrupt to top of priority list • Cannot change priority of non-maskable interrupts • Procedures to increase priority of maskable interrupt: • Set I bit to disable maskable interrupts • Write low byte of the starting interrupt vector address to HPRIO • Clear I bit to re-enable maskable interrupts

  19. Highest Priority Interrupt Register (HPRIO) • PSEL[7:1] – Priority Select Bits • Write the low byte of the starting maskableinterrupt vector to HPRIO to elevate that maskable interrupt to the highest priority • Ex: writing $DE (#%11011110) to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE &$FFDF) Address: $001F

  20. ATD Interrupt Example : ISR • Write an Interrupt Service Routine (ISR) to be run to print out the ATD results when conversion is finished • Other programs still running during the conversion • Continuous conversion • Polling code from our Lab 2: CHECK LDX #ATDSTAT0 BRCLR $00,X #%1000000 CHECK * Wait until conversion completes

  21. ATD Interrupt Example : ISR *Interrupt Service Routine ORG $2000 LDAA ATDDR0H STAA LSTCONV LDAA #$00 *Load D with LSTCONV LDAB LSTCONV LDX #51 *Load x with #51 IDIV *Divides D by X ->D:X XGDX ADDB #$30 STAB V1 *Stores B to v1 XGDX LDAA #10 *Load A with 10 MUL *Multiply A and B (low byte of D) LDX #51 IDIV XGDX ADDB #$30 STAB V2 *Stores B to v2 LDX #STRING1 JSR OUTSTRG LDAA #%00010000 *Scan=0, MULT=0, CC:CA=000 (AN0) STAA ATDCTL5 *Start Conversion by setting ATDCTL5 RTI Define a starting address Read ATD result register Store value to a reserved memory location Convert value and print to screen Writing to ATDCTL5, only convert data from AN0 Ensures that we will get the next interrupt (SCF is cleared) Finally, call RTI to return from the ISR and pull CPU register values back from the stack

  22. ATD Interrupt Example: Setup • Set up interrupt vector table for the ATD Interrupt • Write the address of the first instruction of the ISR ($2000) to ATD interrupt vector ($0FD2) • Enable ATD interrupt • Setting ASCIE bit (ATDCTL2) to enable ATD interrupts (local mask) • Enable global maskable interrupts • Processor is then free to run other code

  23. ATD Interrupt Example: Setup ORG $1000 SEI LDX #$2000 STX $0FD2 LDAA #%10000010 STAA ATDCTL2 LDAA #%00001000 STAA ATDCTL3 LDAA #%10000101 STAA ATDCTL4 LDY #100 L1 DEY BNE L1 CLI LDAA #%00000000 STAA ATDCTL5 Store the address of our ISR ($2000) to the Interrupt Vector for the ATD ($0FD2) Set the ASCIE bit (bit 1 in ATDCTL2) to enable local ATD interrupts Set that only one conversion each sequence Set ATD resolution and prescale Wait for the ATD to fully power up Starting conversion by setting ATDCTL5, Scan=0, MULT=0, CC:CA=000 (AN0) Set I bit to make Interrupt Vector Table changes safe Clear the I-bit to enable all maskableinterrupts

  24. ATD Interrupt Example: Full Code ATDCTL2 EQU $0082 ATDCTL3 EQU $0083 ATDCTL4 EQU $0084 ATDCTL5 EQU $0085 ATDSTAT0 EQU $0086 ATDDR0H EQU $0090 LSTCONV EQU $800 OUTSTRG EQU $FF5E ORG $802 STRING1 FCC "The voltage is " V1 RMB 1 FCC " . " V2 RMB 1 FCC " Volts" FCB $0A,$0D,$04 ORG $1000 SEI LDX #$2000 *Start address of ISR STX $0FD2 *ATD Service Routine Vector LDAA #%10000010 *ADPU = 1, ASCIE=1, ASCIF=0 STAA ATDCTL2 LDAA #%00001000 * one conversion each sequence STAA ATDCTL3 LDAA #%10000101 *Resolution and prescale STAA ATDCTL4 LDY#100 *ATD Converter Startup Delay L1 DEY BNE L1 CLI LDAA #%00000000 *Scan=0, MULT=0, CC:CA=000 (AN0) STAA ATDCTL5 *Start Conversion by setting ATDCTL5 ………… *All kinds of programs Loop ******* *Many other calculations may be performed here ****** JMP Loop SWI END *Interrupt Service Routine ORG $2000 LDAA ATDDR0H STAA LSTCONV LDAA #$00 *Load D with LSTCONV LDAB LSTCONV LDX #51 *Load x with #51 IDIV *Divides D by X ->D:X XGDX ADDB #$30 STAB V1 *Stores B to v1 XGDX LDAA #10 *Load A with 10 MUL *Multiply A and B (low byte of D) LDX #51 IDIV XGDX ADDB #$30 STAB V2 *Stores B to v2 LDX #STRING1 JSR OUTSTRG LDAA #%00010000 *Scan=0, MULT=0, CC:CA=000 (AN0) STAA ATDCTL5 *Start Conversion by setting ATDCTL5 RTI Define Constants(ex: ATDCTL4) Interrupt Service Routine Define Strings and reserve memory Setup ADC and ADC Interrupt Convert value and print to screen Start next conversion Back to main program Run any other code

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