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The EMMA Turn-by-Turn BPM System

The EMMA Turn-by-Turn BPM System. A. Kalinin ASTeC Daresbury Laboratory STFC EMMA Commissioning Workshop Daresbury Laboratory, 21 May 2009. Left. The ‘bunch’ (black) and the EBPM prototype response ( blue ).

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The EMMA Turn-by-Turn BPM System

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  1. The EMMA Turn-by-Turn BPM System A. Kalinin ASTeC Daresbury Laboratory STFC EMMA Commissioning Workshop Daresbury Laboratory, 21 May 2009

  2. Left. The ‘bunch’ (black) and the EBPM prototype response (blue). A flat test bench, the ‘bunch’ trajectory is a 2cm strip line 4cm from the wall. The second pulse is a reflection from the strip line open end. The overshot RC is about 200ps. So, the pickup capacitance is about 4pF. With a ceramic washer, it will be greater. In the cylindrical geometry, it will be again greater. Generator AVM-2-C, scope TDS6124C. Right. At the end of a 2m length RG58cable.

  3. So, x,y position in ~90 pickups: • Single bunch/turn-by-turn, spacing 55ns, up to ~1k turns • In ~2/3 of pickup aperture • Bunch ≤30ps and (16 to 80)pC • Resolution required ≤50um

  4. BPM Noise & Resolution • For the bandwidth 150MHz the 50 input thermal noise is: • The signal-to-noise ratio for a bunch in the 12cm Strip Line BPM is: where 0.7V is the converter output signal measured with beam by oscilloscope. • For lower intensity the signal-to-noise ratio degrades proportionally to intensity. For the intensity 16pC • For the EMMA button electrode pickup of the same angle size, as a strip line pickup, the button electrode sensitivity is worse than of the strip line approximately in ratio strip line length to button diameter times. For diameter 25mm this ratio is 5. It yields: • The pickup aperture is 20mm radius. So, for the intensity 16pC the ultimate BPM resolution is:

  5. Our approach to the EMMA BPM system: • For a bunch, detect and measure and recordeach button pickup signal individually. • Calculate the bunch position in computer. • Using a time delay, multiplex two opposite button pickup signals into a single detecting channel. • Use a pipe-line ADC. • To diminish contribution of a ADC clock time jitter to BPM resolution, make the ADC input pulsestop-flat. • Clock the ADC&Memory by the bunch signalitself. • Convert the button pickup signal into a burstwith a flat top envelope. • To detect the envelope, use a synchronous detector. • Use a Gaussian filter for the detector output to avoid transient ringing. • Delay the ADC clock by a Gaussian filter transition time to sample the envelope on its flat part. • Use a square wave burst. • Manufacture the synchronous detector clock signal from the burst itself.

  6. BPM Block Diagram

  7. Stripline-based Converter

  8. Beam Tests of Analog Processor prototype. KEK ATF 7x10^9e bunch.

  9. Turns & Stop (Last Turn)

  10. Time Diagram

  11. EMMA BPM READOUT • The event is Injection.  • BPM has two parallel Channels.  • Before Injection, asynchronously to it, Write in each Channel a 16bit word: Input Attenuator 4bit, Clock Delay 8bit, Reserved 4bit • Master Reset • With the last turn, the card gives out a common for two Channels READY • Read a common for two channels Number of Turns N=12bit from a counter • Read Position signals and Pedestals: (3+4*N+4) 16bit words (15bit+OVR) from • the FIFO in each Channel with Interface Clock (FWFT, /OE, /REN&RCLK) • Master Reset • Calculate and display turn-by-turn position • For repetitive Injections and some constant beam displacement 1. Scan both Input Attenuators in parallel and read the BPM signals to set the BPM intensity scale; 2. Scan both Clock Delays in parallel and read the BPM signals to observe each Channel analog output pulse and to find an optimal sample moment.

  12. BPM System Status • Circuit design is finished. • Main circuits have been tested with beam. • The system Architecture has been established. • Front-End crates are ordered. • Cables are being laid. • The Front-End card is ready for fabrication except the converter PCB. The fabrication can be started without this PCB. Two companies to fabricate. • A BPM card consist of an Analog Processor PCB (daughter) and an Interface PCB (mother): Analog Processor PCB layout has been designed but needs some work to finish. Then a PCB prototype should be made, populated, tested. Two companies to fabricate. The Interface is most retarded. Now it is under design in a UK company. They will deliver a PCB prototype tested with a controller. Then fabrication.

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