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Esterel and Other Projects

Prof. Stephen A. Edwards from Columbia University presents insights into the Esterel programming language and an innovative compiler developed for it. The presentation covers the mechanics of the Esterel language, showcasing its unique capabilities for managing concurrent systems. It also delves into new compiler infrastructure designed to optimize Esterel, allowing for faster execution and more efficient code generation. Additionally, other ongoing projects related to Esterel are introduced, emphasizing the language's evolving role in embedded systems and real-time applications.

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Esterel and Other Projects

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  1. Esterel and Other Projects Prof. Stephen A. Edwards Columbia University, New York www.cs.columbia.edu/~sedwards

  2. Outline • Part 1 • The Esterel language • My compiler for it (DAC 2000) • Part 2 • New Esterel Compiler Infrastructure • Other projects

  3. The Esterel Language emit B; if C emit D; Force signal B to be present in this cycle Emit D if signal C is present

  4. The Esterel Language await A; emit B; if C emit D; pause Wait for next cycle with A present Wait for next cycle

  5. The Esterel Language loop await A; emit B; if C emit D; pause end Infinite loop

  6. The Esterel Language loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end Run concurrently

  7. The Esterel Language loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end Same-cycle bidirectional communication

  8. The Esterel Language every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Restart when RESET present

  9. The Esterel Language every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Good for hierarchical FSMs

  10. The Esterel Language every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Bad at manipulating data

  11. The New Compiler Esterel every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Step 1: Translate Concurrent Control-Flow Graph

  12. The New Compiler Step 2: Schedule Scheduled CCFG Esterel every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Step 1: Translate Concurrent Control-Flow Graph

  13. The New Compiler Step 3: Sequentialize Sequential Control-Flow Graph Esterel every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Step 1: Translate Step 2: Schedule Concurrent Control-Flow Graph Scheduled CCFG

  14. The New Compiler C Void foo() { switch (st) { 0: if (IN=3) st = 5; goto L5; 1: if (RES) st = 3; goto L8; } L5: switch } Step 4: Generate C Esterel every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Step 1: Translate Step 2: Schedule Step 3: Sequentialize Concurrent Control-Flow Graph Sequential Control-Flow Graph Scheduled CCFG

  15. The New Compiler C Esterel Void foo() { switch (st) { 0: if (IN=3) st = 5; goto L5; 1: if (RES) st = 3; goto L8; } L5: switch } every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end • Generated code is 2 to 100 faster • 1/2 to 1 the size

  16. The New Compiler C Esterel Void foo() { switch (st) { 0: if (IN=3) st = 5; goto L5; 1: if (RES) st = 3; goto L8; } L5: switch } every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end Flow similar to Lin [DAC ‘98]

  17. Step 1: Build Concurrent CFG every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end RESET

  18. Add Threads every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end RESET Fork Join

  19. Split at Pauses every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end RESET 1 1 s 2 2

  20. Add Code Between Pauses every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end RESET 1 s 2 A B C D s=2 s=1

  21. Build Right Thread every RESET do loop await A; emit B; if C emit D; pause end || loop if B emit C; pause end end RESET 1 s 2 A B B C C D s=2 s=1

  22. Step 2: Schedule Add arcs for communication RESET • Topological sort • Optimal scheduling: NP-Complete • “Bad” schedules OK 1 s 2 A B B C C D s=2 s=1

  23. Step 3: Sequentialize • Hardest part: Removing concurrency • Simulate the Concurrent CFG • Main Loop: • For each node in scheduled order, • Insert context switch if from different thread • Copy node & connect predecessors

  24. Context Switching Code Save state of suspending thread s=0 s=1 s=2 s=3 Restore state of resuming thread r 0 1 2

  25. Run First Node RESET 1 s 2 A B B C C D s=2 s=1 RESET RESET

  26. Run First Part of Left Thread RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B 1 s A 2 A B

  27. Context switch: Save State RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B A t=0 t=1

  28. Rejoin RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B A t=0 t=1

  29. Run Right Thread RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B A t=0 t=1 B B C C

  30. Context Switch: Restore State RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B A t=0 t=1 B C 0 1 t

  31. Resume Left Thread RESET 1 s 2 A B B C C D s=2 s=1 RESET 1 s 2 B A t=0 t=1 B C C 0 1 t D C D s=2 s=1 s=2 s=1

  32. Step 3: Finished RESET 1 s 2 A B B C C D s=2 s=1 RESET RESET 1 s 2 B 1 s A 2 A t=0 t=1 B B B C C C 0 1 t D C D s=2 s=1 s=2 s=1

  33. Existing Esterel Compilers Automata V3 [Berry ‘87], Polis [DAC ‘95] switch (st) { case 0: st = 1; break; case 1: Capacity Simulation Speed

  34. Existing Esterel Compilers Logic gates V4, V5 [Berry ‘92, ‘96] A = B && C; D = A && E; Capacity AutomataV3 [Berry ‘87], Polis [DAC ‘95] Simulation Speed

  35. Existing Esterel Compilers Logic gates V4, V5 [Berry ‘92, ‘96] A = B && C; D = A && E; CNET [CASES 2k] Capacity AutomataV3 [Berry ‘87], Polis [DAC ‘95] Simulation Speed

  36. Existing Esterel Compilers New Compiler Logic gates V4, V5 [Berry ‘92, ‘96] CNET [CASES 2k] Capacity Automata V3 [Berry ‘87], Polis [DAC ‘95] Simulation Speed

  37. Speed of Generated Code Average cycle time (ms) Size (source lines)

  38. Size of Generated Code Object code size (K) Size (source lines)

  39. Part 2 Present and Future Work

  40. New Projects • New Esterel compiler • Languages for Device Drivers • Languages for Communication Protocols

  41. ESUIF • New, open Esterel compiler designed for research • Source distributed freely • Based on SUIF2 system (suif.stanford.edu) • Modular construction • Standard compiler approach • Front end builds AST • AST dismantled into intermediate form • Intermediate form translated into low-level code • C code ultimately produced

  42. ESUIF Status • Front-end written, accepts large Esterel examples • Dismantlers partially complete: intermediate form defined • Linker (run statement expansion) to be implemented • Back-end to be implemented

  43. Esterel Compilation Plans • Apply discrete-event simulation techniques • Similar to the CNET compiler • Apply Program Dependence Graph representation • Concurrent representation used in optimizing compilers • Apply “localized partial interpretation” to expand parts of the system into finite-state machines • Techniques will point the way for other synchronous, concurrent languages

  44. Languages for Device Drivers • Device drivers are those pieces of software that you absolutely need that never seem to work • Tedious, difficult-to-write • Ever more important as systems incorporate customized hardware

  45. Best To Date • Thibault, Marlet, and Consel • IEEE Transactions Software Engineering, 1999 • Developed the Graphics Adaptor Language for writing XFree86 video card drivers • Report GAL drivers are 1/9th the size of their C counterparts • No performance penalty

  46. GAL S3 driver (fragment) chipsets S3_911, S3_924; What driver supports port svga index := 0x3d4; Write address, then data port misc := 0x3cc, 0x3c2; register ChipID := sva(0x30); Logical register serial begin Access sequence for register misc[3..2] <= (3,- , -, -, -) W; seq(0x12) <=> (-, PLL1, -, -, -) R/W; end; identification begin Rules for identifying card 1: ChipID[7..4] => (0x8 => step 2, 0x 9 => S3_928); 2: ChipID[1..0] => (0x1 => S3_911, 0x2 => S3_924);

  47. Future Device Driver Work • Develop language for network card drivers under Linux • Study many existing implementations • Develop prototype language, compiler • Explore challenge of porting to other OSes • Apply lessons to other classes of drivers

  48. Languages for Communication Protocols • Many optimizations for implementing protocol code • Fast-path optimization • Collapsing layers • Tedious to implement manually • Tend to obfuscate code • Too high-level to be applied to, say, C code • Domain-specific language would allow these optimizations to be automated

  49. Summary • Esterel language • Esterel compiler based on control-flow graph • ESUIF: New Esterel compiler under development • Languages for Device Drivers • Languages for Communication Protocols

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