Esterel tutorial

1. Esterel tutorial Mike Kishinevsky (Intel) Gerard Berry (Esterel Technology) Satnam Singh (Microsoft) UPC July 5, 2005

2. Outline • Esterel basics • Hardware and software compilation • Verification • Late design changes (ECO)

3. Synchronous languages approach • Time advances in lock step with one or more clocks • Abstraction of synchronous hardware and discrete control software • Deterministic concurrency • Concurrent processes always end up in a unique fix point state • Explicit well controlled non-determinism is allowed for modeling needs • Reactive • No input changes within a cycle => no internal and output changes • unless receivers look into past or emitters emit to the future • Safety: correct-by-construction implementation that can be checked • Convince customers, designers, certification authorities of safety • Solid mathematical foundation • Support formal reasoning, verification • Reviews: Proceedings of the IEEE [Sept. 1991, Jan. 2003]

4. Behavior of Synchronous System Cycle based read inputs compute reaction produce outputs Synchronous = within the same cycle propagate control propagate signals

5. Delay models • Synchronous languages : zero delay • Esterel, Lustre, Argos, SyncCharts, Signal, PBS, etc.. • Behavioral determinism • Choose the right order for dependent actions • Nice algebra => useful idealization Will not discuss today • Asynchronous languages : arbitrary delay • Petri Nets, CSP, Occam, Internet, etc. • Behavioral non-determinism • Determinism for sub-classes (e.g. delay-insensitive, speed-independent) • More complex than synchrony • Real computing and communication: some delay • Any implementation has some inertia and cost • Internal non-determinism is unavoidable • but, does not imply external non-determinism (e.g. RTL logic)

6. Zero delay example: Newtonian Mechanics Concurrency + Determinism Calculations are feasible

7. Predictable delay examples: sound, light, waves • Wait long enough, same result as 0-delay ! • Zero delay and predictable delay are fully compatible • Constructive semantics is the unification • A theory of causality for reactive systems • Clocked digital circuits paradigm

8. Synchronous Reactive Systems Esterel SyncCharts Argos PBS Lustre SCADE Signal Lava signals signals control data values values Esterel v7

9. Signals • Two possible states of a signal during clock cycle • present= emitted by somebody (encoded by “1”) • absent= otherwise (encoded by “0”) • Signal format <present_bit> <value_of_type> • present_bit is reactive (does not keep the value during next cycle) • value is persistent (carry the value to the next cycle) • Signal types • Pure (no value) – control • Value only (no present bit) – data • Valued – control bit (like a valid bit) and a data • Signal location: input, output, input-output, local • Full support for scoping of local signals

10. Combinational emit S if S then … else … end loop Sequential pause await S sustain S Some Esterel statements • Control flow: • Sequence: “;” • Concurrency: “||” • abort • if • loop • Data flow expressions: • ?A < 0 • ?B + ?C • call P() • ?D = f()

11. Sequencing emit A ; emit B ; pause ; emit C

12. Sequencing emit A ; emit B ; pause ; emit C A

13. Sequencing emit A ; emit B ; pause ; emit C A B

14. Sequencing wait for a cycle emit A ; emit B ; pause ; emit C A B

15. Sequencing emit A ; emit B ; pause ; emit C C A B

16. Looping loop emit A ; emit B ; pause ; emit C end loop C A B

17. Looping loop emit A ; emit B ; pause ; emit C end loop C A B

18. Looping loop emit A ; emit B ; pause ; emit C end loop C A B

19. Looping loop emit A ; emit B ; pause ; emit C end loop C A A B

20. Looping loop emit A ; emit B ; pause ; emit C end loop • Loop back in the same cycle • Non-instantaneous body • Loop invariant: cannot reenter if the body still executes C A B A B

21. Decision emit A ; emit B ; pause ; loop if C then emit D else Q end if; if E then emit F end if; pause end loop C C E E D D Q F A F B

22. Concurrency { await A ; emit C || await B ; emit D } ; emit E A B D E C • Start parallel statements in the same cycle • Terminate parallel block once all branches terminated B A C E D A B C D E

23. Preemption abort pause ; pause ; emit A when B ; emit C • Normal termination • Aborted termination • Aborted termination; emit A preempted A C B C B C

24. When to react? await A ; emit B await immediate A ; emit B A A A B B A A A B B • Non-immediate (default) form does not react to signals arrived during the initial instance (before the first tick)

25. When to kill? abort pause; emit A ; pause; emit B when C; emit D weak abort pause; emit A ; pause; emit B when C; emit D C C A D D C C B D A D A • Strong abort (default) kills all emissions during the abort cycle • Weak abort gives signal emissions the last will

26. Four (react, kill) possibilities When to react to A weak abortPwhenA abortPwhenA next abortP when immediateA weak abortP when immediateA now When to kill P next now

27. Esterel more concise than Verilog loop await caseicu_missdo if (notcacheble)then await (normal_ackorerror_ack) else abort await4 normal_ack whenerror_ack end end case(pcsu_powedownand notjmp_e and notvalid_diag_window)do await (pcsu_powerdownandnot jmp_e) end end ; pause end loop Example from S. Edwards

28. Esterel more concise than Verilog Write to memory as soon as Addr and Data have arrived. Wait for memory Latency before iterating. Restart behavior each Replay.

29. Esterel more concise than Verilog Write to memory as soon as Addr and Data have arrived. Verilog = explicit FSM Esterel: write things once { awaitAddr|| awaitData} ; emitWrite(funcW(?Addr,?Data)) ; A D A, D/W( ) D/W( ) A/W( )

30. Esterel more concise than Verilog Write to memory as soon as Addr and Data have arrived. Wait for memory Latency before iterating. Esterel: write things once Verilog = explicit FSM loop { awaitAddr|| awaitData} ; emitWrite(funcW(?Addr,?Data)) ; awaitLatencytick end loop A D A, D/W() D/W() A/W() L=0 X := L-1 X = 0 X > 0 / X:=X-1

31. Local events; concurrency/preemption; hierarchy; parameterization of delays; call things once Global state; state/transition explosion; flat; explicit counters; multiple calls Esterel more concise than Verilog Write to memory as soon as Addr and Data have arrived. Wait for memory Latency before iterating. Restart behavior each Replay. Verilog = explicit FSM Esterel: write things once R loop abort { awaitAddr|| awaitData} ; emitWrite(funcW(?Addr,?Data)) ; awaitLatencytick whenReplay end loop R A D R A, D/W() D/W() A/W() L=0or R X := L-1 X = 0orR X > 0 / X:=X-1

32. SyncCharts = Graphical Esterel SyncChart [C. Andre, …] Esterel code loop [ await A|| await B ] ; emit O each R Implemented in Esterel Studio

33. Extensions in Esterel v7 language Goal: remove the limitations of Esterel v5 much more expressive, but very same semantics • Mix of Esterel imperative and Lustre equational styles • Better modularity, (mild) object orientation • data, interface, and module units, data and interface inheritance • Structured ports, arrays, more signal kinds • value, temp, registered, etc. • Static code replication (for ... dopar) • Support for Moore machines • Numerical encodings • binary, onehot, Gray, etc. • Multi-clock, clock-gating • 100% synthesizableto RTL/C/SystemC, modular optimization

36. ZBT SSRAM SDRAM DDRSDRAM ROM OPB ZBT SSRAMController SDRAMController DDR SDRAMController External BusController OPB Bridge On-ChipPeripheral CoreConnect OPB(On-Chip Peripheral Bus) CoreConnect Processor Local Bus (PLB) Arbiter On-ChipPeripheral 405 PPC I-Cache PLB OPB Bridge D-Cache PLB High-SpeedPeripheral

38. Esterel Studio

39. Code generation VHDL, Verilog -> hardware implementation void uart_device_driver () { ..... } Esterel design uart.c C -> software implementation

40. Serial ATA • New standard for inside-the-box storage connection with cable length <1m • 100% SW compatible “drop in” replacement for ATA with additional capabilities (hot plug) • Fast low voltage differential signaling w/ 8b/10b encoding • 1.5Gbps -> 3.0Gbps -> 6.0Gbps • “Star” topology (point-to-point, no hubs) • Cost competitive with parallel ATA • Long term scalable solution

41. Serial ATA Architecture Transport Translates taskfile accesses to sequences of interface operations. Link Manages interface operations including transmission/reception of frames. SATA Host Controller Transport SW Interface PHY Transmits/receives serial signal and converts to/from digital. Task File Link PHY

42. Esterel: hierarchical managing of complexity

43. How Esterel different from RTL phy_ready pmack /pmack JK-flop mod7 reset counter /pmack clear PMACK 1 1 0 1 1 + adv * suff + ! phy_ready / clear suff 0 = 2 0 set 1 3 0 7 PMWAIT adv pmack pmack clear clear adv adv • Explicit communication via three signals • Hard to ensure proper use in time: reset of data path • forgotten if not phy_ready at last counting cycle

44. The same spec in Esterel is correct-by-construction /* PMACK state */ abort sustainpmack when case not phy_ready case 7 adv end abort /* PMWAIT state */ PMACK /pmack <1> <2> not phy_ready 7 adv • No explicit communication • Compiler does the job, not designer • Behaviors and signals have local scope • If (not phy_ready) then automatic correct reset of counting data path • Sequential events and actions can be embedded into control (e.g. await 7 adv) PMWAIT

45. Verification by simulation

46. Verification with Observers Inputs Observed system System model Observer BUG Outputs BUG is possibly emitted BUG is always emitted Verifier BUG is never emitted

47. Verification engines • 2 proof engines available inside Esterel Studio • Built-in verifier : TiGeR • BDD technique • Prover Plug-in • SAT + numerical techniques • Handles control + data

48. Formal verification Of the OPB slave interface : proving that it won’t cause bus timeouts Proven in less than 2 seconds

49. Three methods • Esterel => FSM => encode => netlist • does not scale • Esterel => netlist (syntax-directed) => optimize • Main method in (v5 compiler) • Optimization both combinational and sequential • Modular compilation to scale (v6, v7) • Esterel => program graph => encode locally => netlist => optimize • Might give better trade-offs and still scale well • Columbia U. compiler (Edwards, …)

50. Syntax directed translation by example loop abort [awaitAddr || awaitData] ; callWrite (?Addr, ?Data) ; await [Latencytick] whenReplay end loop Addr GO SEL RES K0