R&D of interconnections for Belle II and sLHC

1. R&D of interconnections for Belle II and sLHC • R&D projectsatthe MPI semiconductorlaboratory • Requirementsfor ATLAS and Belle II pixeldetectors • Hybrid pixeldetectors versus monolithicsensors • DEPFETs for Belle II • 3D integrationforsLHC

2. ATLAS: Hybrid Pixel Detectors Radiatonhardness (bulkdamage) Fast readoutwithgoodtiming (25 ns) High momentumtracks: material less an issue (but still important) Hybrid pixeldetector (2 tier) & 3D interconnection + Large signal, good S/N + High processing power in each pixel fast, high rate capability + Can be made very radiation hard -Material (Sensor & ASIC, connectivity, tiling) - Large power dissipation (need active cooling -> mass) - Cost driver: interconnection (non- standard high density bump bonding 50µm pitch)

3. p p n+ n n n n p Belle II: Monolithic Detectors Radiation hardness (ionizing) Moderate fast readout (20 µs) Soft tracks: O(1 GeV) < 0.2% X0 required Monolithicactivepixelsensor (DEPFET) Integrate readout electronics (amplification) into sensor + low mass + (almost) no interconnection (but need few ASICs with large pitch > 150µm) - Slow (frame readout, rolling shutter) CMOS Sensors (MAPS) DSM CMOS withepillayerassensor DEPFET FET on fullydepletedbulk +‘standard CMOS’ process + complex CMOS circuit (but limited to NMOS) - small signal, slow collection - Area limited by chip size - non standard double-sided process - simple, one stage amplifier +large signal, fast collection +wafer size sensors

4. DEPFET • Each pixel is a p-channel FET on a completely depleted bulk • A deep n-implant creates a potential minimum for electrons under the gate (“internal gate”) • Signal electrons accumulate in the internal gate and modulate the transistor current (gq ~ 400 pA/e-) • Accumulated charge can be removed by a clear contact (“reset”) • Fully depleted: • large signal, fast signal collection • Low capacitance, • internal amplification: => low noise • High S/N even for thin sensors (50µm) • Rolling shutter mode (column parallel) for matrix operation • 20 µs frame readout time • => Low power (only few lines powered)

5. DEPFET Performance Fe55: 1.6 e- rms noise, Room temperature ! 10 ms shaping time Low noise: x-ray spectroscopy and imaging High speed -> noise ~ t-1/2 At 50MHz: ENC < 40e (for 50ns readout ) For tracking: even thinned (but fully depleted) detectors have excellent S/N S/N > 200 measured for d=450 mm S/N ~ 40 achievable for d=50 mm Position resolution < 2 mm in beam tests

6. DEPFET for Belle II 2 layers: @1.4(2.2) cm Pixels: 50 x 50(75) µm 75µm thick 0.18% X0 Thickness:75 µm total of 8 Mpx Barcelona (Uni, CNM, Ramon Lull), Bonn, Heidelberg, Giessen, Göttingen, Karlsruhe, Krakow, Munich (MPI, TU, LMU), Prague, Santander, Santiago de Compostella Valencia, KEK VERTEX 2010 Loch Lomond June 10, 2010 Power consumption in sensitive area: 0.1W/cm² => air-cooling sufficient

7. Sensor Thinning ? Need thin (50µm-75µm) self supporting all silicon module Process backside e.g. structured implant etching of handle wafer (structured) Thinning of top wafer (CMP) Processing diodes and large mechanical samples Belle II module Wafer bonding SOI process

8. ASICs for control and readout Switcher (Heidelberg) • DHP (Bonn) • Common mode correction • Pedestal subtraction • (16 events average) • DCD offset compensation (2bit) • Switcher control • Test chip (1/2) • 32 channels • C4 bump bonding • Submitted IBM 90nm DCD (Heidelberg) In order to get a very compact module layout bump bonding is needed for the interconnection to the DEPFET sensor Moderate pitch 150 to 200 µm Use standard processes whenever available • Produced in UMC 180nm

9. Interconnection: BumpBonding DCD (UMC 180nm) : MPW delivered with bumps (SnAgCu, pitch 180µm) DHP (IBM 90nm) MPW deliveredwith C4 bumps (SnAg, pitch 200µm) Switcher: nobumpingofferedby AMS for MPW => in house(Heidelberg)

10. Cu UBM compatible with DEPFET technology? Sensor teststructespreparedat HLL CNM, Barcelona sputterbarierandseedlayer Cuelectroplating SputterandCuplatingispresentlybeingimplementedas backend processattheHLL (also forotherprojects: XFEL, sLHC…) Correlation of leakage currents before and after UBM

11. Future: 3D integration Performance of DEPFET sensors ultimately limited by slow frame readout BX identification not possible, long integration time Hybrid pixel detectors offer high processing power per pixel Need to reduce material, cost (fine pitch bump bonding) and power 3D integration: Evolution of hybrid pixels high density, low mass interconnection of several (thin) layers (tiers) ‘quasi-monolithic detectors’ Si pixel sensor • Optimized Module Design: Less material: • thin sensors and ASICs • higher fill factor • Reduced cantilever • backside connectivity • slim edges • Radiation hardness: • thin sensors improve CCE • (rtapping)

12. MPI 3D R&D Program • Build demonstrator using ATLAS pixel chip (FE-I2/3) and thin pixel sensors made by MPI (complete wafers with FEI2, FEI3 chips available!) • Use interconnection technology allowing postprocessing • Interconnection with SLID and ICV technology by FraunhoferIZM • Demonstration of postprocessing of standard ASICs with via last • R&D Issues: • Technology: compatible with sensors, ASICs? • Interconnection quality: e.g. capacitance • Yield & Costs. • Production in industry. • Material (copper layer).

13. Sensors In house production on FZ-SOI material (2 kWcm) Detector wafer thickness 75 µm and 150 µm p- and n-type material p-spray insulation Udep 20V and 80V (before irradiation) ~ 100% CCE at 1016 n/cm² 75 µm

14. IZM SLID Process • Alternative to bump bonding (less process steps “low cost” (IZM)). • Small pitch possible (<< 20 mm, depending on pick & place precision). • Stacking possible (next bonding process does not affect previous bond). • Wafer to wafer and chip to wafer possible. • However: no rework!

15. Inter Chip Vias ICV = Inter Chip Vias Etching (Bosch process) Insulation, filling with tungsten Electroplating, metallisation • Hole etching and chip thinning • Via formation with W-plugs. • Face to face or die up connections. • 2.5 Ohm/per via (including SLID). • No significant impact on chip performance • (MOS transistors). Back thinning Electroplating, metallisation

16. SLID Pad 27x360 mm2 50% SLIDcoverage SLID Pad 27x58 mm2 10% SLID coverage Al BCB 25 um 20 um Cu3Sn 30 um 15 um Al SiO2 Tests of metal dummies Test of SLID interconnection with metal dummies. • Aim: determine the feasibility of the SLID inter-connection within the parameters we need for the ATLAS pixels. • Test of the mechanical strength as a function of different area coverage by the SLID pads • Test the SLID efficiency varying the dimensions of the SLID pads • Study the SLID efficiency when degrading the planarity of the structure underneath the pads • Determine the alignment precision between single “chip” and “detector” wafer • Investigate the BCB isolation capability between the detector and chip surfaces

17. Test interconnections (SLID) Special test wafers for SLID tests Chains of SLID connections

18. Problems Shorts: No problems with small pads (30 x 30 µm² and 50 x 50 µm²) However, many shorts for larger pads (80 x 80 µm²) Amount of tin needs to be adjusted according to pad size and coverage (pressure) Pad size 80x80 µm² Pitch 100 µm • Bad connection: • Some chips fell off • Differences in height: some chips not in proper contact! • Chips came from different wafers (some 20 µm tolerances!) • Different chip sizes lead to variations of local pressure • Use chips from same wafers (or make sure that they have equal thickness • Look even at radial position of chip on wafer (wafer thickness spherical) • Use only chips of same size

19. 1 3 2 Project Status Cu electroplating of FEI3 chips for SLID UBM done Dummy pads needed for extra mechanical strength Pixel pads • Identification of Target area for ICV etching: • Investigation with a FIB analysis to identify possible areas for TSV etching: • Central region between pads: filling structures with superimposed tungsten plugs and metal layers • Covered by top metal layer in some pads • ICV directly over the pad area after having etched away the top aluminum layer Dummy pads (Type A)

20. Next Steps • Sensor/ASIC interconnection using SLID • ASIC thinned to 200 µm • No vias, integrated fan-out on sensor for service connection • Sensor/ASIC interconnection using SLID • -ASIC thinned to 50 µm • -vias for service connections (fan-outs for redundancy) • Future: SLID interconnection of sensors/ 3D FEI4 • Sensor/ASIC interconnection using SLID • ASIC thinned to 200 µm • No vias, integrated fanout on sensor for service connection • Sensor/ASIC interconnection using SLID • -ASIC thinned to 50 µm • -vias for service connections (fanouts for redundancy) • Future: SLID interconnection of sensors/ 3D FEI4

21. Summary DEPFETs for Belle II: precisionvertexdetectoroptimizedforlowmomentumtracks emphasison lowmassandlow power radiationhardupto 10 Mrad fast framereadoutforlowoccupancydespitehighbackground thin, selfsupporting all-silicondetectors lownumberof large pitchinterconnects useindustrystandardbumpbonding 3D integrationofsensorand ASIC forsLHC SLID interconnectionas alternative tofinepitchbumpbonding viasforbacksideconnectivity (4-side buttable) 3D integrationusingvia last postprocessing thinsensorsforradiationhardness (1016 n/cm²)