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1. Introduction 2. I – V relationship : Conceptual Approach

MOSFET. 1. Introduction 2. I – V relationship : Conceptual Approach 3. I – V relationship : Analytical Approach 4. Threshold Voltage ( V T ) and transconductance ( g m ) 5. Second Order Effects 6. Applications of MOSFET-based Devices. Expected Outcomes

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1. Introduction 2. I – V relationship : Conceptual Approach

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  1. MOSFET 1. Introduction 2. I – V relationship : Conceptual Approach 3. I – V relationship : Analytical Approach 4. Threshold Voltage (VT) and transconductance (gm) 5. Second Order Effects 6. Applications of MOSFET-based Devices.

  2. Expected Outcomes • At the end of the lectures on MOSFETs, you should be able to : • Describe the structure of n- and p-channel MOSFETs. • Explain the concept of the operation of MOSFETs. • Derive a simple analytical model of the MOSFET to relate the I-V characteristics, transconductance, etc., to the structural parameters of the MOSFET. • Explain qualitatively some of the second order effects of MOSFETs. • Perform analysis of simple MOSFET circuits.

  3. Reading assignment • D A Neamen, Semiconductor Physics and Devices, Third Edition, McGraw-Hill (2003), pp. 483 – 490, 496 – 501, 524 – 533.

  4. 1. Introduction • In an n-channel MOSFET, the substrate is p-type, while heavily doped n-type regions form the “source” and “drain” regions. • The electrode on top of the thin oxide (dielectric) layer is called the “gate”. • The source terminal is the source of the carriers that will flow through the channel to the drain terminal. • In this n-channel device, electrons flow from the source to the drain. • Conventional current therefore enters from the drain terminal and flows out of the source terminal. • Note that usually there is also a contact to the substrate of “body” of the MOSFET, and it is usually grounded. Basic structure of an n-channel MOSFET.

  5. Circuit symbols for an n-channel enhancement mode MOSFET Cross-sectional view of an n-channel enhancement-mode MOSFET. • In the above MOSFET, when no voltage is applied to the gate (VGS= 0), there is no inversion channel in the silicon under the gate. The source and drain regions are not connected electrically, and no current flows from the drain to the source, even if a voltage is applied between the drain and the source.

  6. If a positive voltage that is greater than the threshold is applied at the gate (where VGS > VT), the vertical electric field through thin gate dielectric causes the formation of an inversion layer at the silicon surface beneath the gate. => the source and the drain are connected through the inversion layer, and a current can flow between the source and the drain if a bias (VDS) is applied between the drain and the source. • The MOSFET is called an enhancement-mode MOSFET because it is normally off. A conduction channel is formed and a current can flow between the drain and the source only when a gate voltage (greater than the threshold voltage) is applied. • The principle of operation of the MOSFET can be understood approximately in terms of a water analogy, as shown by the animation below. WaterFET animation

  7. The above figure shows a depletion-mode MOSFET. When zero voltage is applied to the gate, an inversion layer already exists in the silicon under the gate. This acts as a channel connecting the source and the drain. A current will flow if a voltage is applied between the drain and the source. • To remove the inversion layer, and hence to stop the current flow, a negative voltage has to be applied to the gate. Note that the threshold voltage is negative (even though the device has a p-type substrate.) • Since most of the MOSFETs in both analog and digital circuit are enhancement-mode devices, it is assumed that all the MOSFETs discussed in this course are enhancement mode MOSFETs unless otherwise specified. Cross-sectional view and circuit symbol of an n-channel depletion-mode MOSFET.

  8. In a p-channel MOSFET, heavily doped p+ regions make up the source and drain regions. The substrate is n-type. • When a negative voltage whose magnitude is greater than the threshold voltage (which is also negative) is applied to gate, an inversion layer of holes is formed. Holes flow from the source to the drain when a voltage VDS is applied. Circuit symbols for a p-channel enhancement mode MOSFET Cross-sectional view of a p-channel enhancement-mode MOSFET.

  9. 2. I-V relationship : Conceptual Approach Consider an n-channel enhancement mode MOSFET (i) Cut-off or subthreshold region • VGS is zero or less than VT, and VDS is a small positive voltage. • In this situation, no electron inversion layer is formed and the drain junction is reverse biased, therefore the drain current is ideally zero.

  10. (ii) Linear region • When VGS > VT , an electron inversion layer is formed in the silicon under the gate, and forms a conducting channel between the source and the drain. • Underneath the inversion channel, there is a thick depletion region. • For smallVDS, the channel thickness is approximately constant and has the characteristics of a resistor (or conductor). Therefore, the change in the drain current, ΔID, is proportional to the change in the drain voltageΔVDS, i.e., ΔID = gdΔVDS, (2.1) where gd is the conductance of the channel.

  11. When the gate bias VGS is increased, more charges are deposited on the gate, which in turn induce more electrons in the inversion layer. • The channel conductance gd depends on the amount of inversion layer charge, and the inversion layer charge is a function of VGS. • This therefore results in the modulation of the channel conductance, which determines ID, by VGS.

  12. (iii) Saturation region • As VDS is increased, there is a significant voltage drop along the channel from the drain to the source. As a result, the voltage drop across the oxide, between the gate and the channel near the drain junction edge decreases. The inversion charge density near the drain decreases and the channel tapers towards the drain end. • The incremental conductance of the channel decreases as VDS gets larger. • IDincreases at a slower rate with VDS.

  13. When VDS increases further to the point where the voltage drop across the oxide, between the gate and the channel at the drain edge, is equal to the threshold voltage VT , the inversion charge density is zero at the drain edge. • This is called the “pinch-off” condition. The inversion layer is pinched-off at the drain edge. • At the point of pinch-off, the incremental conductance is zero. the slope of IDvs.VDS curve becomes zero for this condition. • There is no more increase in ID with the increase of VDS => The drain current is said to be “saturated”. • We define “VDS(sat)” as the drain voltage which produces pinch-off condition at the drain junction edge, i.e., VGS – VDS(sat) = VT, or VDS(sat) = VGS – VT (2.2)

  14. When VD > VDS(sat), the pinch-off point in the channel moves toward the source junction edge. • Electrons enter the channel at the source and travel (by drift) through the channel towards the drain. When they reach the pinch-off point, the electrons are injected into the depletion region where they are swept by the E-field into the drain. • For a given MOSFET and at a given VGS, VDS(sat) is constant, as given by eqn (2.2). • If the change in the channel length (ΔL) due to the movement of the pinch-off point is small compared to the original channel length (L), then the resistance of the inversion channel is approximately constant. As the drain current IDis a function of the voltage drop in the channel (= VDS(sat)) and the channel resistance, ID would therefore be constant for drain voltages VD > VDS(sat).

  15. We have noted earlier that the inversion channel charge is a function of the gate bias VGS(for VGS > VT). By changing VGS, we modulate the channel resistance (or conductance). • Therefore, each time when VGS is changed, we get a different ID-VDS characteristic. By varying VGS, we can generate a family of curves for the n-channel enhancement-mode MOSFET, as shown in the figure below. MOSFET Simulation applet

  16. P-channel (enhancement mode) MOSFET • In a p-channel MOSFET, VDS, VGS and VT are all negative. • Holes are the majority carriers. They flow from source to drain. therefore ID is also negative (with the direction as defined in the figure).

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