Chapter 6 Introduction to Digital Electronics - PowerPoint PPT Presentation

chapter 6 introduction to digital electronics n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Chapter 6 Introduction to Digital Electronics PowerPoint Presentation
Download Presentation
Chapter 6 Introduction to Digital Electronics

play fullscreen
1 / 81
Chapter 6 Introduction to Digital Electronics
346 Views
Download Presentation
mavis
Download Presentation

Chapter 6 Introduction to Digital Electronics

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Chapter 6Introduction to Digital Electronics Microelectronic Circuit Design Richard C. JaegerTravis N. Blalock Microelectronic Circuit Design McGraw-Hill

  2. Chapter Goals • Introduce binary digital logic concepts • Explore the voltage transfer characteristics of ideal and nonideal inverters • Define logic levels and logic states of logic gates • Introduce the concept of noise margin • Present measures of dynamic performance of logic devices • Review of Boolean algebra • Investigate simple transistor, diode, and diode-transistor implementations of the inverter and other logic circuits • Explore basic design techniques of logic circuits Microelectronic Circuit Design McGraw-Hill

  3. Brief History of Digital Electronics • Digital electronics can be found in many applications in the form of microprocessors, microcontrollers, PCs, DSPs, and an uncountable number of other systems. • The design of digital circuits has progressed from resistor-transistor logic (RTL) and diode-transistor logic (DTL) to transistor-transistor logic (TTL) and emitter-coupled logic (ECL) to complementary MOS (CMOS) • The density and number of transistors in microprocessors has increased from 2300 in the 1971 4-bit 4004 microprocessor to 25 million in the more recent IA-64 chip and it is projected to reach over one billion transistors by 2010 Microelectronic Circuit Design McGraw-Hill

  4. Ideal Logic Gates • Binary logic gates are the most common style of digital logic • The output will consist of either a 0 (low) or a 1 (high) • The most basic digital building block is the inverter Microelectronic Circuit Design McGraw-Hill

  5. The Ideal Inverter The ideal inverter has the following voltage transfer characteristic (VTC) and is described by the following symbol V+ and V- are the supply rails, and VH and VL describe the high and low logic levels at the output Microelectronic Circuit Design McGraw-Hill

  6. Logic Level Definitions An inverter operating with power supplies at V+ and 0 V can be implemented using a switch with a resistive load Microelectronic Circuit Design McGraw-Hill

  7. Logic Voltage Level Definitions • VL – The nominal voltage corresponding to a low-logic state at the input of a logic gate for vi = VH • VH – The nominal voltage corresponding to a high-logic state at the output of a logic gate for vi = VL • VIL – The maximum input voltage that will be recognized as a low input logic level • VIH – The maximum input voltage that will be recognized as a high input logic level • VOH – The output voltage corresponding to an input voltage of VIL • VOL – The output voltage corresponding to an input voltage of VIH Microelectronic Circuit Design McGraw-Hill

  8. Logic Voltage Level Definitions (cont.) Note that for the VTC of the nonideal inverter, there is now an undefined logic state Microelectronic Circuit Design McGraw-Hill

  9. Noise Margins • Noise margins represent “safety margins” that prevent the circuit from producing erroneous outputs in the presence of noisy inputs • Noise margins are defined for low and high input levels using the following equations: NML = VIL – VOL NMH = VOH – VIH Microelectronic Circuit Design McGraw-Hill

  10. Noise Margins (cont.) • Graphical representation of where noise margins are defined Microelectronic Circuit Design McGraw-Hill

  11. Logic Gate Design Goals • An ideal logic gate is highly nonlinear that attempts to quantize the input signal to two discrete states, but in an actual gate, the designer should attempt to minimize the undefined input region while maximizing noise margins • The input should produce a well-defined output, and changes at the output should have no effect on the input • Voltage levels of the output of one gate should be compatible with the input levels of a proceeding gate • The gate should have sufficient fan-out and fan-in capabilities • The gate should consume minimal power (and area for ICs) and still operate under the design specifications Microelectronic Circuit Design McGraw-Hill

  12. Dynamic Response of Logic Gates • An important figure of merit to describe logic gates is their response in the time domain • The rise and fall times, tf and tr, are measured at the 10% and 90% points on the transitions between the two states as shown by the following expressions: V10% = VL + 0.1ΔV V90% = VL + 0.9ΔV = VH – 0.1ΔV Microelectronic Circuit Design McGraw-Hill

  13. Propagation Delay • Propagation delay describes the amount of time between a change at the 50% point input to cause a change at the 50% point of the output described by the following: • The high-to-low prop delay, τPHL, and the low-to-high prop delay, τPLH, are usually not equal, but can be described as an average value: Microelectronic Circuit Design McGraw-Hill

  14. Dynamic Response of Logic Gates Microelectronic Circuit Design McGraw-Hill

  15. Power Delay Product • The power-delay product (PDP) is use as a metric to describe the amount of energy required to perform a basic logic operation and is given by the following equation when P is the average power dissipated be the logic gate: Microelectronic Circuit Design McGraw-Hill

  16. Review of Boolean Algebra NOT Truth Table OR Truth Table AND Truth Table NOR Truth Table NAND Truth Table Microelectronic Circuit Design McGraw-Hill

  17. Logic Gate Symbols and Boolean Expressions Microelectronic Circuit Design McGraw-Hill

  18. Diode Logic • Diodes can with resistive loads to implement simple logic gates Diode OR gate Diode AND gate Microelectronic Circuit Design McGraw-Hill

  19. Diode Transistor Logic • Since diode gates are limited to AND and OR functions, the diodes can be combined with transistors to complete the basic logic functions such as the following NAND gate Microelectronic Circuit Design McGraw-Hill

  20. NMOS Logic Design • MOS transistors (both PMOS and NMOS) can be combined with resistive loads to create single channel logic gates • The circuit designer is limited to altering circuit topology and width-to-length, or W/L, ratio since the other factors are dependent upon processing parameters Microelectronic Circuit Design McGraw-Hill

  21. NMOS Inverter with a Resistive Load • The resistor R is used to “pull” the output high • MS is the switching transistor • The size of R and the W/L ratio of MS are the design factors that need to be chosen Microelectronic Circuit Design McGraw-Hill

  22. Load Line Visualization • The following illustrates the operation of the NMOS output (vDS) characteristics where the following equation describes the load line Microelectronic Circuit Design McGraw-Hill

  23. NMOS with Resistive Load Design Example • Design a NMOS resistive load inverter for • VDD = 3.3 V • P = 0.1 mW when VL = 0.2 V • Kn = 60 μA/V2 • VTN = 0.75 V • Find the value of the load resistor R and the W/L ratio of the switching transistor MS Microelectronic Circuit Design McGraw-Hill

  24. Example continued • First the value of the current through the resistor must be determined by using the following: • The value of the resistor can now be found by the following which assumes that the transistor is on or the output is low: Microelectronic Circuit Design McGraw-Hill

  25. Example Continued • For vI = VL = 0.2V, the transistor’s vGS will be less than the threshold voltage, therefore it will be operating in the triode region. Using the linear equation for a MOSFET, the W/L ratio can be found: Microelectronic Circuit Design McGraw-Hill

  26. On-Resistance of MS • The NMOS resistive load inverter can be thought of as a resistive divider when the output is low, described by the following expression: Microelectronic Circuit Design McGraw-Hill

  27. On-Resistance of MS (cont.) When the NMOS resistive load inverter’s output is low, the On-Resistance of the NMOS can be calculated with the following expression: Note that Ron should be kept small compared to R to ensure that VL remains low, and also that its value is nonlinear which has a dependence on vDS Microelectronic Circuit Design McGraw-Hill

  28. Noise Margin Analysis • The following equations can be used to determine the various parameters needed to determine the noise margin of NMOS resistive load inverters Microelectronic Circuit Design McGraw-Hill

  29. Load Resistor Problems • For completely integrated circuits, R must be implemented on chip using the shown structure • Using the given equation, it can be seen that resistors take up a large area of silicon as in an example 95kΩ resistor Microelectronic Circuit Design McGraw-Hill

  30. Using Transistors in Place of a Resistor • NMOS load w/ a) gate connected to the source b) gate connected to ground c) gate connected to VDD d) gate biased to linear region e) a depletion mode NMOS Note that a) and b) are not useful Microelectronic Circuit Design McGraw-Hill

  31. Static Design of the NMOS Saturated Load Inverter Schematic for a NMOS saturated load inverter Cross-section for a NMOS saturated load inverter Microelectronic Circuit Design McGraw-Hill

  32. NMOS Saturated Load Inverter Design Strategy • Given VDD, VL, and the power level, find IDD from VDD and power • Assume MS off, and find high output voltage level VH • Use the value of VH for the gate voltage of MS and calculate (W/L)S of the switching transistor based on the design values of IDD and VL • Find (W/L)L (load transistor) based on IDD and VL • Check the operating region assumptions of MS and ML for vo = VL • Verify design with a SPICE simulations Microelectronic Circuit Design McGraw-Hill

  33. NMOS Saturated Load Inverter Design Example • Design an saturated load inverter given the following specifications: Microelectronic Circuit Design McGraw-Hill

  34. NMOS Saturated Load Inverter Design Example • First find VH Microelectronic Circuit Design McGraw-Hill

  35. NMOS Saturated Load Inverter Design Example • For vo = VL,MS is off (triode region) and ML is in saturation, find the W/L ratios of the two transistors Microelectronic Circuit Design McGraw-Hill

  36. NMOS Saturated Load Inverter Design Noise Margin Analysis • The basic noise margin equations are still the same as for previous inverters, but there are different expressions for the components The equations can be written as a quadratic equation,but an iterative process must be used to solve for VOL and VTNL 1) Choose an initial VOL 2) Calculate the corresponding VTNL 3) Update VOL 4) Repeat 2 and 3 until the system converges Microelectronic Circuit Design McGraw-Hill

  37. NMOS Inverter with a Linear Load Device • This alternative inverter has a load transistor that is biased with VGG defined by the following: • This causes the load transistor to operate in the linear region Microelectronic Circuit Design McGraw-Hill

  38. NMOS Inverter with a Depletion-mode Load • With the addition of a depletion-mode NMOS (VTH < 0V), it is possible to configure an inverter as shown • VGSL = 0 V for this configuration meaning that ML is always operating in saturation Microelectronic Circuit Design McGraw-Hill

  39. Design of a NMOS Inverter with a Depletion-mode Load • To find (W/L)L given iDL: • To find (W/L)S where VH = VDD use the same technique as used for the resistor load inverter: Microelectronic Circuit Design McGraw-Hill

  40. Noise Margins of a NMOS Inverter with a Depletion-mode Load The first two equations assume the MS is saturated and ML is in triode The last two equations assume the MS and ML are in triode Microelectronic Circuit Design McGraw-Hill

  41. NMOS Inverter Summary • Resistive load inverter takes up too much area for and IC design • The saturated load configuration is the simplest design, but VH never reaches VDD and has a slow switching speed • The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply for the load gate • The depletion-mode NMOS load requires the most processing steps, but needs the smallest area to achieve the highest speed, VH = VDD, and best combination of noise margins Microelectronic Circuit Design McGraw-Hill

  42. Typical Inverter Characteristic Microelectronic Circuit Design McGraw-Hill

  43. NOR Gates Simplified switch model for the NOR gate with A on Two-input NOR gate Microelectronic Circuit Design McGraw-Hill

  44. NAND Gates Simplified switch model for the NOR gate with A and B on (right) Two-input NAND gate (left) Microelectronic Circuit Design McGraw-Hill

  45. NAND Gate Device Size Selection • The NAND switching transistors can be sized based on the depletion-mode load inverter • To keep the low voltage level to be comparable to the inverter, the desired RON of MA and MB must be 0.5RON of MS,Inverter • This can be accomplished by approximately doubling the (W/L)A and (W/L)B • The sizes can also be chosen by using the design value of VL and using the following equation: Microelectronic Circuit Design McGraw-Hill

  46. NAND Gate Device Size Selection (continued) • Two sources of error that arise are the facts that VSB and VGS of the two transistors do not equal. These factors should be considered for proper gate design • The technique used to calculate the size of the load transistor for the depletion-mode load inverter is the exact same as for this NAND gate Microelectronic Circuit Design McGraw-Hill

  47. Layout of the NMOS Depletion-Mode NOR and NAND Gates Microelectronic Circuit Design McGraw-Hill

  48. Complex NMOS Logic Design An advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates The circuit in the figure has the logic function: Y = A + BC + BD Microelectronic Circuit Design McGraw-Hill

  49. Complex Logic Gate Transistor Sizing • There are two ways to find the W/L ratios of the switching transistors • Using the worst case (longest) path and choosing the W/L ratio such that the RON of the multiple legs match similar to the technique used to find the W/L ratios in the NAND Gate • Partitioning the circuit into series sub-networks, and make the equivalent on-resistances equal Microelectronic Circuit Design McGraw-Hill

  50. Complex Logic Gate Transistor Sizing The figure on the left shows the worst case technique to find the sizes where (W/L)S=2.06 is the reference inverter ratio for this technology and the longest path is 3 transistors are in series The figure on the right shows the partitioning technique to find the sizes which gives two 4.12/1 ratios in series which is 2(2.06/1) Microelectronic Circuit Design McGraw-Hill