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Understanding MicroMIPS Instruction Execution and Data Path Mechanics

This guide provides a comprehensive overview of the instruction execution process in MicroMIPS, where computers execute instructions sequentially. It covers the instruction fetch, decode, and execute cycles, highlighting various instruction formats including R-format and I-format operations. Essential elements such as the ALU, branching, jumping, and control signal generation are explained. The document also details the performance analysis of the single-cycle MicroMIPS design, including the timing of instruction access, register read/write, and ALU operations, culminating in a clear depiction of its architecture.

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Understanding MicroMIPS Instruction Execution and Data Path Mechanics

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  1. 13 Instruction Execution Steps • A simple computer executes instructions one at a time • Fetches an instruction from the loc pointed to by PC • Interprets and executes the instruction, then repeats

  2. 13.1 A Small Set of Instructions Fig. 13.1 MicroMIPS instruction formats and naming of the various fields. Seven R-format ALU instructions (add, sub, slt, and, or, xor, nor) Six I-format ALU instructions (lui, addi, slti, andi, ori, xori) Two I-format memory access instructions (lw, sw) Three I-format conditional branch instructions (bltz, beq, bne) Four unconditional jump instructions (j, jr, jal, syscall)

  3. op 15 0 0 0 8 10 0 0 0 0 12 13 14 35 43 2 0 1 4 5 3 0 fn 32 34 42 36 37 38 39 8 12 The MicroMIPS Instruction Set Copy Arithmetic Logic Memory access Control transfer Table 13.1

  4. 13.2 The Instruction Execution Unit Fig. 13.2 Abstract view of the instruction execution unit for MicroMIPS. For naming of instruction fields, see Fig. 13.1.

  5. 13.3 A Single-Cycle Data Path Fig. 13.3 Key elements of the single-cycle MicroMIPS data path.

  6. lui imm An ALU for MicroMIPS Fig. 10.19 A multifunction ALU with 8 control signals (2 for function class, 1 arithmetic, 3 shift, 2 logic) specifying the operation.

  7. 13.4 Branching and Jumping (PC)31:2 + 1 Default option (PC)31:2 + 1 + imm When instruction is branch and condition is met (PC)31:28 | jta When instruction is j or jal (rs)31:2 When the instruction is jr SysCallAddr Start address of an operating system routine Update options for PC Fig. 13.4 Next-address logic for MicroMIPS (see top part of Fig. 13.3).

  8. 13.5 Deriving the Control Signals Table 13.2 Control signals for the single-cycle MicroMIPS implementation. Reg file ALU Data cache Next addr

  9. Control Signal Settings Table 13.3

  10. Instruction Decoding Fig. 13.5 Instruction decoder for MicroMIPS built of two 6-to-64 decoders.

  11. Control Signal Generation Auxiliary signals identifying instruction classes arithInst = addInst  subInst  sltInst  addiInst  sltiInst logicInst = andInst  orInst  xorInst  norInst  andiInst  oriInst  xoriInst immInst = luiInst  addiInst  sltiInst  andiInst  oriInst  xoriInst Example logic expressions for control signals RegWrite = luiInst  arithInst  logicInst  lwInst  jalInst ALUSrc = immInst  lwInst  swInst AddSub = subInst  sltInst  sltiInst DataRead = lwInst PCSrc0 = jInst  jalInst  syscallInst

  12. Fig. 10.19 Fig. 13.4 addInst Control subInst jInst . . . . . . sltInst Putting It All Together Fig. 13.3

  13. 13.6 Performance of the Single-Cycle Design Instruction access 2 ns Register read 1 ns ALU operation 2 ns Data cache access 2 ns Register write 1 ns Total 8 ns Single-cycle clock = 125 MHz R-type 44% 6 ns Load 24% 8 ns Store 12% 7 ns Branch 18% 5 ns Jump 2% 3 ns Weighted mean  6.36 ns Fig. 13.6 The MicroMIPS data path unfolded (by depicting the register write step as a separate block) so as to better visualize the critical-path latencies.

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