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Unit 2 Reviews on Logic Elements

Unit 2 Reviews on Logic Elements. 2.1 Decoders and Encoders. 3-to-8 line decoder The i th output is 1 if the input binary value is equal to i. 4-to-10 line decoder. In general a n-to-2 n decoder can generate the all 2 n minterms

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Unit 2 Reviews on Logic Elements

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  1. Unit 2 Reviews on Logic Elements Department of Communication Engineering, NCTU

  2. 2.1 Decoders and Encoders Department of Communication Engineering, NCTU

  3. 3-to-8 line decoder • The i th output is 1 if the input binary value is equal to i Department of Communication Engineering, NCTU

  4. 4-to-10 line decoder Department of Communication Engineering, NCTU

  5. In general a n-to-2n decoder can generate the all 2n minterms • Because an n-input decoder generates all of the minterms of n variables, n-variable functions can be realized by ORing together selected minterm outputs from a decoder Department of Communication Engineering, NCTU

  6. An encoder performs the inverse function of a decoder • E.g. 8-to-3 priority encoder • If more that one input is 1, the highest number determines the output • D is 1 if any input is 1, otherwise d is 0 Department of Communication Engineering, NCTU

  7. 2.2 Register and Register Transfers Department of Communication Engineering, NCTU

  8. A 4-bit register is composed of 4 D-type FFs which share a common clock, clear (Clr) and chip enable (CE) Department of Communication Engineering, NCTU

  9. The symbol notation for a 4-bit register Department of Communication Engineering, NCTU

  10. Data are passed from one register to another. In this case, whether Ai or Bi is sent to Di depends on En Department of Communication Engineering, NCTU

  11. A 8-bit register with tri-state output enable (En), and its corresponding symbol Department of Communication Engineering, NCTU

  12. Registers use output enable (for releasing data) and chip enable (for accepting data) to transfer data on a bus Department of Communication Engineering, NCTU

  13. Accumulator : the output of adder is fed back as one of a addend Department of Communication Engineering, NCTU

  14. 2.3 Shift Registers Department of Communication Engineering, NCTU

  15. A shift register is a register whose data can be shifted right or left • A 4-bit right-shift register Department of Communication Engineering, NCTU

  16. The timing diagram of a 4-bit right shift register Department of Communication Engineering, NCTU

  17. A right-shift register with inverted rotation feedback • Two possible output patterns which depend on the initial state • This is called Johnson counter Department of Communication Engineering, NCTU

  18. 2.4 Design of Binary Counters Department of Communication Engineering, NCTU

  19. A synchronous counter is a counter whose FFs are all driven by a clock. While for a asynchronous counter, the output of FF serves as a driving clock of the next FF • A 3-bit synchronous counter implemented with T-FFs Department of Communication Engineering, NCTU

  20. Design the functions of TC , TB , and TA with a state table and a truth table • First, draw a stable which lists the present state and the next state, then draw the truth table of the functions Department of Communication Engineering, NCTU

  21. Logic minimizations with the Karnaugh map Department of Communication Engineering, NCTU

  22. For D-FFs, DA is equal to the next state of FF A. So we only need a state table for counters designed with D-FFs Department of Communication Engineering, NCTU

  23. An alternative design with D-FFs Department of Communication Engineering, NCTU

  24. Design of up-down counter • The state table and the state graph of a up-down counter Department of Communication Engineering, NCTU

  25. The logic functions of inputs • One can verify the function by setting U=0 and D=1, or vice versus. For example, U=0 and D=1 Department of Communication Engineering, NCTU

  26. A up-down counter synthesized with D-FFs Department of Communication Engineering, NCTU

  27. Design of loadable counter with count enable Department of Communication Engineering, NCTU

  28. The next-state equations Department of Communication Engineering, NCTU

  29. Design of loadable up-dn counter with count enable? • Realize this counter with GAL 22V10 • Due on the next meet Department of Communication Engineering, NCTU

  30. 2.5 Counter of Other Sequences Department of Communication Engineering, NCTU

  31. A five state counter • Define the next states of three unused states 001、101、110 as unspecified • The counter can be realized with T-FFs • T =present state’next state • List the truth table for the next states of • Use the Karnaugh map Department of Communication Engineering, NCTU

  32. Notice that T = Q+  Q • So, first design Q+ = f (A,B,C) • Use Karnaugh map for Q=0 and Q=1, respectively • For Q=0, have T = Q+ • For Q=1, have T = (Q+ )’ Department of Communication Engineering, NCTU

  33. Department of Communication Engineering, NCTU

  34. After simplification • Notice that even if the next state of 001，101 and110 are not specified at the beginning, they are assigned certain values implicitly while being used as the don’t care conditions for circuit simplifications Department of Communication Engineering, NCTU

  35. Circuit realization Department of Communication Engineering, NCTU

  36. The effects of don’t care conditions • When CBA=001, TC TB TA = 110, then C+B+A+ =111 • When CBA=101, TC TB TA = 011, then C+B+A+ =110 • When CBA=110, TC TB TA = 101, then C+B+A+ =011 • The final counter Department of Communication Engineering, NCTU

  37. An alternative design with D-FFs • This is much easier since DC = C+, DB = B+ and DA = A+ • So, the functions are Department of Communication Engineering, NCTU

  38. 2.6 Derivation of Flip-Flop Input Equations Department of Communication Engineering, NCTU

  39. In counter design, we mainly derive the input equations of FFs. This can be done either with the true table of the present states and the next states, or with the next-state map Department of Communication Engineering, NCTU

  40. Department of Communication Engineering, NCTU

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  42. 2.7 Programmable Logic Array Department of Communication Engineering, NCTU

  43. A programmable logic array (PLA) with n inputs and m outputs is a device that can realize m functions of n variables by means of sum-of-products. • A PLA consists of an AND array with n input lines and a OR array with m output lines Department of Communication Engineering, NCTU

  44. An example OR Array AND Array Department of Communication Engineering, NCTU

  45. 2.8 Programmable Array Logic Department of Communication Engineering, NCTU

  46. Different PLA, the product term of a programmable array logic (PAL) can not be shared by multiple OR gates. • Besides, the number of inputs of the OR is fixed and limited, e.g. Department of Communication Engineering, NCTU

  47. A commercial device : GAL20V8B Department of Communication Engineering, NCTU

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