Unit 2 Reviews on Logic Elements. 2.1 Decoders and Encoders. 3-to-8 line decoder The i th output is 1 if the input binary value is equal to i. 4-to-10 line decoder. In general a n-to-2 n decoder can generate the all 2 n minterms

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Unit 2 Reviews on Logic Elements

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In general a n-to-2n decoder can generate the all 2n minterms • Because an n-input decoder generates all of the minterms of n variables, n-variable functions can be realized by ORing together selected minterm outputs from a decoder Department of Communication Engineering, NCTU

An encoder performs the inverse function of a decoder • E.g. 8-to-3 priority encoder • If more that one input is 1, the highest number determines the output • D is 1 if any input is 1, otherwise d is 0 Department of Communication Engineering, NCTU

A synchronous counter is a counter whose FFs are all driven by a clock. While for a asynchronous counter, the output of FF serves as a driving clock of the next FF • A 3-bit synchronous counter implemented with T-FFs Department of Communication Engineering, NCTU

Design the functions of TC , TB , and TA with a state table and a truth table • First, draw a stable which lists the present state and the next state, then draw the truth table of the functions Department of Communication Engineering, NCTU

Design of up-down counter • The state table and the state graph of a up-down counter Department of Communication Engineering, NCTU

The logic functions of inputs • One can verify the function by setting U=0 and D=1, or vice versus. For example, U=0 and D=1 Department of Communication Engineering, NCTU

A five state counter • Define the next states of three unused states 001、101、110 as unspecified • The counter can be realized with T-FFs • T =present state’next state • List the truth table for the next states of • Use the Karnaugh map Department of Communication Engineering, NCTU

Notice that T = Q+ Q • So, first design Q+ = f (A,B,C) • Use Karnaugh map for Q=0 and Q=1, respectively • For Q=0, have T = Q+ • For Q=1, have T = (Q+ )’ Department of Communication Engineering, NCTU

After simplification • Notice that even if the next state of 001，101 and110 are not specified at the beginning, they are assigned certain values implicitly while being used as the don’t care conditions for circuit simplifications Department of Communication Engineering, NCTU

The effects of don’t care conditions • When CBA=001, TC TB TA = 110, then C+B+A+ =111 • When CBA=101, TC TB TA = 011, then C+B+A+ =110 • When CBA=110, TC TB TA = 101, then C+B+A+ =011 • The final counter Department of Communication Engineering, NCTU

An alternative design with D-FFs • This is much easier since DC = C+, DB = B+ and DA = A+ • So, the functions are Department of Communication Engineering, NCTU

A programmable logic array (PLA) with n inputs and m outputs is a device that can realize m functions of n variables by means of sum-of-products. • A PLA consists of an AND array with n input lines and a OR array with m output lines Department of Communication Engineering, NCTU

An example OR Array AND Array Department of Communication Engineering, NCTU

Different PLA, the product term of a programmable array logic (PAL) can not be shared by multiple OR gates. • Besides, the number of inputs of the OR is fixed and limited, e.g. Department of Communication Engineering, NCTU