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Ph.D. defense

The measurement of the Lorentz angle in the BTeV pixel detectors: the new PCI based DAQ, the setup and the results. Lorenzo Uplegger. Ph.D. defense. Milano 26/01/2004. BTeV main goals. The BTeV experiment will investigate one of the most fundamental

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Ph.D. defense

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  1. The measurement of the Lorentz angle in the BTeV pixel detectors: the new PCI based DAQ, the setup and the results Lorenzo Uplegger Ph.D. defense Milano 26/01/2004

  2. BTeV main goals The BTeV experiment will investigate one of the most fundamental problems of elementary particle physic, the CP violation. Some of the most important aspects of this kind of physics are: • CP violation in b and c quark sector • Measurement of the mixing phenomena of the B0s meson • Study of the beauty baryons • Research of new phenomena beyond the Standard Model • Definitively the measurement of the elements of the • Cabibbo-Kobayashi-Maskawa matrix

  3. BTeV detector layout BTeV main goals

  4. Pixel vertex detector • Pixel dimensions 50 mm x 400 mm • Plane dimensions 10 cm x 10 cm • Gap between stations 4.25 cm • Total number of stations 30 • Total number of planes 60

  5. Pixel vertex detector • The pixel detector will operate in a high magnetic field, so the position • reconstructed by the pixels is shifted by the effect of the Lorentz • force acting on the charge carriers in the silicon. • The effect on the carriers depends upon the different irradiation • doses absorbed by the detector. • Since the irradiation dose is greater close to the beam than in the • outer regions of the pixel plane, different corrections must be applied • in order to keep a good track resolution. • Thus I worked on the development of a setup which allowed me to • measure the Lorentz angle.

  6. DAQ for pixels • Since the pixel detectors will be tested in a 120 GeV beam this • year, the work was mainly directed to build a complete read-out • system for test-beam studies but flexible enough to allow laboratory • bench-test studies and in particular the Lorentz angle measurement. • Furthermore the DAQ system has been designed with enough flexibility to accommodate the m-strip readout chip as well. • ( I would recall that my group is responsible for the construction • of the m-strip forward tracker ) • I covered many aspects of the design and implementation of this new • PCI based DAQ and I will first discuss all the features required by • the test-beam needs.

  7. Test-beam main goals • Measure the spatial resolution of the sensors before and after • irradiation • Time-Walk studies • Test the read-out chip (ROC) in the real BTeV working conditions • data-driven mode • Build events using only the temporal information (time-stamp) • associated to pixel cells without the aim of an external trigger

  8. Experimental setup

  9. telescope • FPIX1 • preFPIX2Tb • FPIX0 detectors under test Experimental setup

  10. Read-out architecture Detector Mezzanine-card PCI card Detector Mezzanine-card PCI card DAQ dedicated PC Readout & processes monitor PCI extender Detector Mezzanine-card PCI card

  11. Experimental setup DATA BCO CLOCK, READ CLOCK… DATA BCO CLOCK, READ CLOCK …

  12. DATA DATA Experimental setup

  13. DATA DATA Experimental setup

  14. DATA DATA DATA DATA DATA DATA Experimental setup PCI BUS

  15. Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Data10 Data11 Data12 DAQ main features EVENT Readout process

  16. noise noise DAQ main features Readout process

  17. Data1 Data4 Data6 Data7 Data8 Data10 Data11 noise noise noise DAQ main features Readout process

  18. Data1 Data1 Data2 Data3 Data4 Data5 Data4 Data6 Data7 Data7 Data9 Data10 Data10 Data11 Data12 noise noise noise Data1 Data4 Data7 Data10 noise DAQ main features ????? Readout process Data8

  19. 132 ns Data1 Ts 5 Data1 Ts 5 Data2 Ts 5 Data2 Ts 5 Data3 Ts 5 Data3 Ts 5 Data4 Ts 5 Data4 Ts 5 Data5 Ts 5 Data5 Ts 5 Data6 Ts 5 Data6 Ts 5 Data7 Ts 5 Data7 Ts 5 Data8 Ts 5 Data8 Ts 5 Data9 Ts 5 Data9 Ts 5 Data1 Ts 2 Data2 Ts 2 Data3 Ts 2 Data4 Ts 2 Data5 Ts 2 Data6 Ts 2 Data7 Ts 2 Data8 Ts 2 Data9 Ts 2 Data1 Ts 2 Data1 Ts 2 Data2 Ts 2 Data2 Ts 2 Data4 Ts 2 Data4 Ts 2 Data6 Ts 2 Data6 Ts 2 Data7 Ts 2 Data7 Ts 2 Data8 Ts 2 Data8 Ts 2 Data3 Ts 2 Data5 Ts 2 Data9 Ts 2 DAQ main features BCO 6 5 4 3 2 1 time-stamp

  20. DAQ main features The read out system works in absence of an external trigger The data collection from the different pixel detectors is therefore asynchronous The DAQ must assemble the events in asynchronous mode Events are built using the time-stamp information

  21. ALTERA FPGA Firmware • This read-out is data driven: data are collected as • soon as there is a hit above threshold in the detector • It is important that the data flux from pixels to PCI is not hampered • by the read-out system, which transfers data to the PC. • In order to balance the different acquisition rates between the • detectors, PCI cards and the PC, we took particular care in the design • of the • FPGA firmware • PC Read-out software

  22. ALTERA FPGA Firmware

  23. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  24. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  25. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  26. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  27. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  28. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  29. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  30. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  31. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  32. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  33. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  34. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  35. PCI card working mechanism Bank0 Bank1 Readout process Shared memory Reset interrupt Consumer FPGA Interrupt handler Disk writer Time

  36. PCI card working mechanism • This process of periodic memory swap and transfer to a shared • memory continues indefinetely. • We have several PCI cards playing this swap game in parallel: • in order to be able to build events at a later stage, • we needed a syncronization mechanism to keep the event builder • as simple as possible. • By synchronizing the swapping of all the memories we can build • events in a very simple and immediate way.

  37. Readout working mechanism Banks 0 1 Each PCI card has its own interrupt-handler process listening for the memory-full signal Interrupt handler A Let’s suppose, for instance, that the PCI card C is the first being filled up. Interrupt handler B • The PCI card C redirect immediately the data flux to the other empty memory Interrupt handler C • The interrupt handler of the PCI card C forces the other cards to swap and then starts flushing its content to the host PC Interrupt handler n

  38. Readout working mechanism Banks 0 1 Each PCI card has its own interrupt-handler process listening for the memory-full signal Interrupt handler A Let’s suppose, for instance, that the PCI card C is the first being filled up. Interrupt handler B • The PCI card Credirect immediately the data flux to the other empty memory Interrupt handler C • The interrupt handler of the PCI card C forces the other cards to swap and then starts flushing its content to the host PC • The other cards start flushing their • (partially) filled memory banks to the • host PC. Interrupt handler n

  39. C0 A0 B0 … n0 Readout working mechanism Banks 0 1 • This architecture guarantees that events • with contiguous time-stamps belong to • buffers which are also contiguous in the • read-out process. Interrupt handler A Interrupt handler B Interrupt handler C Interrupt handler n

  40. C1 A1 B1 … n1 Readout working mechanism Banks 0 1 • This architecture guarantees that events • with contiguous time-stamps belong to • buffers which are also contiguous in the • read-out process. Interrupt handler A Interrupt handler B Interrupt handler C C0 A0 B0 … n0 Interrupt handler n

  41. BUFi BUFi+1 Readout working mechanism Banks 0 1 • This architecture guarantees that events • with contiguous time-stamps belong to • buffers which are also contiguous in the • read-out process. Interrupt handler A • Events with the same time-stamp are • contained within the boundaries of this • overall buffer (BUFi), or at least in the • next one, BUFi+1, but not in BUFi+2, • making the event-builder an • implementation of a sorting algorithm. Interrupt handler B Interrupt handler C C0 A0 B0 … n0 C1 A1 B1 … n1 Interrupt handler n

  42. Event builder Shared Memory (unordered data) Event buffer (ordered data) Event Builder Event Timestamps: • Every hit with a new timestamp starts a new event (column) in a buffer • Other hits with the same time-stamp are appended to the right column • in the buffer • When the analysis of the BUFFER i+1 is over, it is reasonable • to assume that there are no more data related to an event that begun • in BUFFER i.

  43. DAQ conclusion • We built a DAQ system that will be used for the upcoming test-beam • I covered many aspects in the design and implementation of this DAQ: • I collaborated on the software development • I personally took care of the FPGA programming • I was then able to use this read-out system to measure the Lorentz • angle in the silicon pixel detector • I will show now the measurement and the results that I obtained…

  44. Lorentz angle Optical Fiber Focusing Lens Blue LED Light ~2mm DZ 280mm QL Pixel detector B E XL X0 DX QL effective= DX/DZ

  45. Experimental setup

  46. Experimental setup Optical Fiber Focusing Lens B E Blue Light

  47. Lorentz displacement B(KGauss) BiasE(V) Experimental setup • Pixel size in the Y direction = 400mm • Pixel size in the X direction = 50mm • B  parallel to the Y direction • Bias E along the Z direction Lorentz displacement mainly in the X direction  50 mm X 400 mm Y

  48. C.o.G. = 50 mm 400 mm Y X Measurements • The blue light illuminated several cells in two different columns. • With a threshold scan I was able to know the charge collected in each cell. • Knowing the charge, I could calculate the Center of Gravity of the cluster: • a bidimensional point, X and Y.

  49. X-measurements We expect displacements linearly proportional to the magnetic field and symmetric respect to the sign of the B field. Instead here is what I measured Dx [mm] B < 0 B > 0 B KGauss

  50. Y-measurements Displacements are present even with B  0. Also in this case they are in the same direction reversing the magnetic field. Dx [mm] B < 0 B > 0 B KGauss

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