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Ph.D. Dissertation Defense

Ph.D. Dissertation Defense

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Ph.D. Dissertation Defense

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  1. VARIABLE SWING Optimal Parallel LINKsMinimal Power, Maximal density for parallel links configurationsClaudia P.Barreraadvisor: fouad kiamilevPhD committee: Allen Barnett guang gao mayra sarmiento Ph.D. Dissertation Defense

  2. Outline

  3. Outline - Introduction

  4. Motivation

  5. Motivation • Mobility • Mobile devices require low power, high data rates • Increasing multimedia applications • Higher definition displays • Smaller sizes • Battery life

  6. Motivation • Size • Transistor size still decreasing • Moore’s Law still valid • Higher computational capabilities on-chip but interconnect requirements constrain the size of the devices

  7. Motivation Source: Intel Corporation - http://www.intel.com/technology/timeline.pdf

  8. Motivation • Speed • Required higher data rates • Multimedia applications • High Performance Computing • Off-chip speed is the bottleneck for high speed communications 2003 ITRS (International Technology Roadmap for Semiconductors) roadmap for on-chip and off-chip speed. Taken from http://www.ieee.org/organizations/pubs/newsletters/leos/oct04/summer.html

  9. Problem Statement POWER SAVINGS • Design Stage • Need of communication between A and B • Length • Speed • Power MAXIMUM LINE LENGTH / SPEED 8 – 16mA - TX current 3.5mA - TX current 0.1mA - TX current CML LVDS WhisperBus Standard Fixed TX Power A B Communication If length is long, a high TX power is OK But if the distance between A and B is short, there will be a Waste of Power.

  10. Problem Statement • Design Stage • Maximum data rate allowed in the communication • Serial • Parallel Data Rate: X Data Rate: 4X P P SERDES Serializer - Deserializer B A SERDES SERDES P P

  11. Problem Statement • Design Stage • Maximum data rate allowed in the communication • Serial • Parallel Data Rate: X Data Rate: 4X P P SERDES Bandwidth Increment 4X 4X P P A B P P P P 4X 4X Then, what is the problem with parallel links?

  12. Problem Statement • Space… 1 2 A B

  13. Problem Statement • Space… A B

  14. Problem Statement • Space… A B A Bandwidth Limitation by maximum number of wires that can be routed

  15. Previous Work • Optimization based on free parameters • Geometry w d t h εr

  16. Previous Work • 3D approach to eliminate crosstalk • Not feasible for a PCB

  17. Previous Work • Jitter equalization technique that induces a data dependent delay to compensate for crosstalk jitter • Quantification of crosstalk-induced jitter from the mutual capacitance and inductance between two adjacent lines

  18. Serial Power Optimization TechniqueVSMPL POWER OPTIMIZATION ALGORITHM BASED ON AN ACCELERATED BIT ERROR RATIO (BER) MEASUREMENT • Set transmitter power to where BER~10-4 • Increment power setting • Measure current BER • Repeat steps 2 and 3 several times • Fit a line through the data points • Estimate the transmitter power setting required to achieve the target BER J. Kramer

  19. Serial Power Optimization TechniqueVSMPL BER 2 BER 1 Accelerated BER Tester Power setting 1 Power setting 2 Power set to 3 Power 3 =F(BER1,BER2)

  20. VSMPL in a bus configuration Accelerated BER Tester 1 2 BER increases 1 2 1 2 BER increases

  21. Contribution of this work • Based on accelerated BER measurement: • Simple technique that reduces crosstalk • Novel technique using anti-coupling capacitors • Up to 87% reduction • Reflections are minimized • Termination resistor is adjusted dynamically • Once crosstalk and reflections are minimized: • Channels can be treated as serial links. • Serial power optimization technique can be applied MINIMAL POWER, MAXIMUM DENSITY FOR A PARALLEL LINK

  22. Outline - Crosstalk

  23. Transmission line modeling w t εr h Microstrip Stripline Wire Pair

  24. Transmission line modeling

  25. Coupling between transmission lines 1 2 εr M M

  26. Coupling between transmission lines Aggressor Victim Near End Far End Near End Far End

  27. Coupling between transmission lines Vb Time RT Far End noise Near End noise RT: Rising Time TD: Time Delay Vb Near End Far End TD Time RT 2 x TD

  28. Coupling between transmission lines C14 C24 C13 C12 C23 C34 1 2 3 4 C11 C22 C33 C44

  29. Differential Signaling V1 1 + Vo=V1-V2 2 - V2 Advantages: Tolerance to ground offsets Low voltage High immunity to common noise

  30. Crosstalk in differential signaling The problem of crosstalk in differential signaling is that generates a non common noise. The effect of electromagnetic fields is higher on the closest line V1-V2 (V1+b*Vn)-(V2+d*Vn) d* > b* V1 V2 Vn V1 V2 Vn Differential pair with a quiet line routed closely Noise effect in a differential pair when an active line is routed closely

  31. Crosstalk in differential signaling C14 Aggressor Victim C24 + - + - C13 C23 Transmission lines are linear systems Superposition can be applied VV+ VV- VA+ VA- Victim Aggressor VA+=-VA- VV+=VA+*(C13)+VA-*(C14) VV-=VA+*(C23)+VA-*(C24) VV=VV+-VV-

  32. Anti-Coupling Capacitances C14 C24 Using superposition principle… C13 VV+=VA+*(C13)+VA-*(C14) C23 +VA-*(Anti-C13)+VA+*(Anti-C14) + - + - VV-=VA+*(C23)+VA-*(C24) VA+=-VA- VV=VV+-VV- Anti-C24 +VA-*(Anti-C23)+VA-*(Anti-C24) Anti-C14 Anti-C23 Anti-C13

  33. Reflections • Reflections happen when the transmission line is not matched. Output impedance Characteristic Impedance Zo Termination Impedance

  34. Optimization algorithm BERT + • Tune the termination resistor on the receiver based on the BER measurement on the link at low power. • Tune the anti-coupling capacitances: • Turn on the victim line at low power (so that BER is in the order of 10-4) • Turn on one neighbor at the highest power. The BER in the victim line will increase due to crosstalk noise. • Tune anti-coupling capacitance until minimum BER is reached. • Review impedance matching for the line. Repeat 1 and 2 until stable. • Apply serial power optimization to each line. Anti-C23 - Anti-Cb Anti-C23 + -

  35. Outline – Testing, Simulation Platforms and Results

  36. Testing Platform BERT Labview Card Anritsu Digital Data Analyzer RX TX PRBS Generator

  37. Testing Results

  38. Testing Results 35uA 48uA 63uA

  39. Simulation Platform W-Element Matrix

  40. Experiments setup 6.5mils 4mils Aggressor 4mils Victim 5.7 mils 100mm

  41. Extracted transmission line parameters

  42. Transistor level simulation

  43. Simulation Platform

  44. Effect of anti-coupling capacitors • Differential pairs routed as close as manufacturing technology allows • One aggressor • One victim • Measured the differential voltage on the victim and report the highest noise (voltage) • Placed 4 capacitors and started to change the value of one of them until the minimum crosstalk was reached.

  45. Effect of anti-coupling capacitance • By adding the anti-coupling capacitance, the crosstalk is reduced up to 78%.

  46. Required spacing to achieve same performance • Increase spacing between the 2 lines by 1X and measure the highest noise. • Repeat previous step until performance of anti-coupling capacitors is reached

  47. Required spacing to achieve same performance • To achieve the same crosstalk reduction, the spacing between differential lines must be 6X Anti-coupling capacitances performance

  48. FFT of the signal induced by crosstalk In the quiet line • -Minimum spacing between differential • channels • -- 5X spacing between differential • channels • -- Minimum spacing between differential • Channels using anti-coupling cap Power noise on the victim line is reduced significantly when an anti-coupling capacitance is used. The effect of adding the anti-coupling capacitors is actually better than spacing the channels by the rule of thumbs given by the literature.

  49. Far end noise – time domain Aggressor -- No anti-coupling capacitances -- Effect of anti-coupling capacitances in time domain Victim

  50. Effect of anti-coupling capacitances in induced jitter -- No anti-coupling capacitances -- Effect of anti-coupling capacitances 140ps 17ps