Multi-Channel waveform generator for radar-Preliminary Design REVIEW Group G: Qi “Trey” Zhong Wei Cai
Overview The goal of this project is to design a reconfigurable multi-channel waveform generator for the radar system in CReSIS. There are two parts in the system: * Software in host PC * FPGA logic design for DDS (digital directed synthesizer)
Organization Chart • The design tasks can be divided into 3 major parts: • Firmware design • Software design • Host PC to FPGA communication.
Technical Specs • FPGA: • Cyclone V GX • 77k programmable logic elements • 4884 kilobit memory • Host software: • Development tool: LabVIEW 2012 • Host PC module: • NI PXIe-8135 • Communication between PC and FPGA: • RS232 • DDS: • AD9915 • 2.5 GSPS internal clock speed • 135 pHz frequency tuning resolution • 16-bit phase tuning resolution • 12-bit amplitude scaling • 32-bit parallel datapath interface • Multichip synchronization
Technical Specs • Waveform Configuration: • Signal bandwidth: 150-600MHz • Linear frequency modulation: Chirp (positive frequency rate) • Pulse width range: 1ms ~ 30 ms • Number of pre-sum signals: 1 ~ 64 • Pulse repetition frequency: 1~ 20 kHz • Amplitude modulation: Up ramping, down ramping, Tukey • Configuration speed: > 160 MHz
System Overview The block diagram on the left is the overview of entire multi-channel waveform generator system. The design for EECS 502 is only the daughter board. The design will continue after the end of this semester to complete the rest of the system.
Implementation - Firmware
Implementation - Software
Test Plan • Software section test plan: • Before integration, host software should be tested by configuring several different parameters on the GUI. The values for those parameters will be translated to the a bit file by the host software. The data in the bit file should be checked bit by bit to verify the correctness. • Firmware section test plan: • Before bridging firmware with the host software, all the functions on firmware should be tested. Different output waveforms will be tested using oscilloscope. All the parameters can be manually adjusted in the VHDL code and the RAM initialization file. • Host to FPGA test plan: • The host to FPGA communication will be tested using a separate code that solely implements the serial communication and related protocol. The received value will be verified using Chipscope Pro. • System test plan: • The entire system will be put together and test will be conducted to verify the functionality of each parts. Oscilloscope and Chipscope Pro will be used to verify the correctness of the output.