AIDA design review Davide Braga Steve Thomas ASIC Design Group 09 October 2008. X10 stage - comparator. Comparator threshold adjustment to reduce offset Clamping of the x10 gain stage performed by latched comparator to avoid saturation and hence big current spikes.
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ASIC Design Group
09 October 2008
Minimum value: Vth_ min~=7mV ~=9800eV
(Noise after x10gain stage expected to be σn~=3.5mV → 5σn=17.5mV)
Built-in feature (not selectable) to avoid noise on comparator output: comparator fires at:
Vhyst now set to ~10mV
Most signal would saturate the x10 stage output, causing big (and long!) variations in current
This can be avoided clamping the amplifier to a unity-gain configuration after the comparator has fired
The comparator responsible for the clamping must be latched not to let the amplifier come back to the x10 gain configuration
A timed signal will reset the latch once the signal has disappeared
Another measure has been taken to reduce current oscillation in the comparator by inserting a dummy branch which counterbalances the drop in current consumption in the device
When the reset comes off it causes “small” activity in the shaper, which is enough to fire the comparator and also to be store on the peak hold.
The comparator must be masked and the peak hold could be set in hold mode to decouple it from the shaper output
“left to right” channel layout, with LEC/MEC and HEC in parallel
Grid distribution of power supply (“Horizontal” and “vertical”) to minimize impedence and voltage fluctuation across the chip
which gives C~4fF
Injected charge Q=CV~12fC=75ke for single wire
“Dummy” wires have opposite polarity signals. Electric field drops as r2 for a dipole, giving much lower coupling capacitance