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EECE579: Digital Design Flows. Usman Ahmed Dept. of ECE University of British Columbia. Implementing Digital Circuits. Digital Circuit Implementation Approaches. Custom. Semicustom. Cell-based. Array-based. Standard Cells. Gate Arrays Structured ASICs. FPGA's. Macro Cells.

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eece579 digital design flows

EECE579: Digital Design Flows

Usman Ahmed

Dept. of ECE

University of British Columbia

implementing digital circuits
Implementing Digital Circuits

Digital Circuit Implementation Approaches

Custom

Semicustom

Cell-based

Array-based

Standard Cells

Gate Arrays

Structured ASICs

FPGA's

Macro Cells

Compiled Cells

implementing logic circuits

Design Capture

Behavioral

HDL

Pre-Layout Simulation

Structural

Logic Synthesis

Floorplanning

Post-Layout Simulation

Placement

Physical

Circuit Extraction

Routing

Tape-out

Implementing Logic Circuits

Design Iteration

standard cell design
Library of cells that implement different gates

Cells can have different width but all cells have same height

(hence Standard Cells)

Many variants of the same cell

Standard Cell Design
standard cell design5
Logic Synthesis

Transform the HDL description into library cells

Placement

Where to place a cell ?

Routing

Connect the placed cells.

Standard Cell Design
standard cell design6
Optimizations:

Gate Resizing

Buffer Insertion

In-place Re-synthesis

Standard Cell Design
standard cell design summary
Used only for the high-speed or low-power applications

Very expensive, and time consuming

(> $2M just for the mask costs)

Very high re-spin cost

Standard Cell Design: Summary
fpgas
FPGAs
  • FPGA: Field-Programmable Gate Array
what s inside an fpga

Logic Blocks

- used to implement

logic

- lookup tables and

flip-flops

Altera: LABs

Xilinx: CLBs

What’s Inside an FPGA?
what s inside an fpga13
What’s Inside an FPGA?

I/O Blocks

- interface off-chip

- can usually support

many I/O Standards

logic block

Bit-Stream

Logic Block:

Basic Logic Gate: Lookup-Table

Function of each lookup table can be configured by shifting in bit-stream.

Inputs

logic clusters
Logic Clusters

Several lookup tables are grouped into “clusters”

- Typically 8 to 10 lookup

tables per cluster

Connections between lookup tables in the same cluster are fast

Connections between lookup tables in different clusters are slow

reconfigurable logic
Reconfigurable Logic:

Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

reconfigurable logic19
Reconfigurable Logic:

Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

implementing systems in an fpga
Implementing Systems in an FPGA

FPGA Fabric

Embedded memories

Embedded PowerPC

Hardwired multipliers

Xilinx Vertex-II Pro

High-speed I/O

slide21
Advantages of FPGAs:
  • "Instant Manufacturability": reduces time to market
  • Cheaper for small volumes because you don’t need to pay for fabrication
      • means you don’t need to be a big company to make a chip
  • Relaxes Designers -> relaxed designers live longer!

Disadvantages of FPGAs:

  • Slower than custom or standard cell based chips
  • Cannot get as much circuitry on a single chip
  • Today: ~ 1M gates is the best you can do

~ 200 MHz is about as fast as you can get

  • For large volumes, it can be moreexpensive than gate arrays and custom chips
structured asics
Structured ASICs
  • Combines good features of FPGAs and Standard Cell ASICs
logic blocks
Logic Blocks
  • Choices
    • Fine Grained
      • Basic gates: NAND, NOR, XOR, FF etc.
    • Medium Grained
      • Lookup Tables
    • Coarse Grained
      • Multi-input, Multi-output blocks (e.g., PLAs)
  • Configurability
    • SRAM cells
    • Vias
      • Lower Level (e.g., between M1 and M2)
      • Upper Level (Via stacks brought up to the configurable layers)
routing fabrics
Routing Fabrics
  • Metal and Via Programmable
    • More flexibility, more efficiency
    • Employed in most structured ASIC offerings
  • Via Programmable
    • Regular, easy to manufacture
    • Metal is fixed and every segment may not be fully utilizable,

→ Can be Inefficient

implementing logic circuits30

Design Capture

Behavioral

HDL

Pre-Layout Simulation

Structural

Logic Synthesis

Floorplanning

Post-Layout Simulation

Placement

Physical

Circuit Extraction

Routing

Tape-out

Implementing Logic Circuits

Design Iteration