Preparation for Chip Testing

Preparation for Chip Testing Chia-Hsiang YangAdvisor: Prof. Dejan MarkovićApril 10, 2009

Road to Testing • After (even before) getting the chip dies, there are lots of things to do before testing… Assembly PCB board package chip die wire-bonding ASIC board Test Setup

Package Data Sheet SSM P/N CPG10018 A1

Socket/Chip PCB Footprint 13 12 11 10 9 8 7 6 5 4 3 2 1 A 75 77 79 81 83 86 89 90 93 95 97 98 100 B 73 76 78 80 82 85 87 91 94 96 99 1 2 C 72 74 84 88 92 3 4 D 70 71 5 6 E 68 69 7 8 F 65 66 67 9 10 11 G 64 62 63 13 12 14 H 61 60 59 17 16 15 J 58 57 19 18 K 56 55 21 20 L 54 53 42 38 34 24 22 M 52 51 49 46 44 41 37 35 32 30 28 26 23 N 50 48 47 45 43 40 39 36 33 31 29 27 25 • Ceramic PGA • SSM P/NCPG10018 (15 × $23.37) • lead count (pins): 100 • Test socket • 3M ZIF socket 13×13 matrix (2×$51.00) A1 Top view (as footprint)

Bonding Diagram • Cost $650 for 20 chips

PCB Board Layout 7500 mil • Layers: 6 • Material: FR4 420 mil 3590 mil • Minimum space: 5 mil • Minimum hole size: 10 mil

Altium Designer • Installed on dsp server • Tutorial: Help -> Getting Started -> Getting Started with PCB Design PCB Library Schematic Library

Plane Splitting • Signals are routed on Top layer and Bottom Layer • Internal planes are usually used for power/gnd • We can split internal planes into many planes for different signals Internal plane 4 Internal plane 3

FPGA Aided Verification • IBOB board and BPS design environment • Test pattern generation and output data capturing through block RAMs (in place of the pattern generator and logic analyzer) • Z-DOK+ connectors provide data rate of 500 Mbps • I/O Interface between client PC and IBOB board in Matlab/Simulink environment RS232 interface (memory access) RS232 ZDOK+ IBOB board ASIC board IBOB board To increase access speed between User terminal and IBOB Board, Ethernet interface might be used in the future ASIC board Parallel IV cable (program)

IBOB Board • FPGA-based processing board • Xilinx Virtex-II Pro 2VP50 FPGA • I/O interface • 2x ZDOK+ 40 differential connectors • 80x GPIO headers (4 banks) with selectable IO voltage (1.5/1.8/2.5/3.3) • 1x MDR 40 differential pair connector • 2x CX4 10Gbps high-speed serial connectors • 1x RS232 interface • 1x 10/100 RJ45 Ethernet interface • 2x SMA IO • 2x 512k x 36-bit SRAMs 2x ADC boards IBOB board

I/O Interface Mapping • GPIO: Note the sequence on the board • SMA: Mislabeled on the board • ZDOK+

ZDOK+ Connector • Tyco Electronics, Adapter P/N: 6367555-3 • Free samples provided • 40 differential pairs • Data rates up to 6.250 Gb/s (But the FPGA I/O limits data rate to about 500 Mb/s) F20 F1 Z1 Z6 W1 W6 A1 A20

ZDOK+ Schematic • 40 differential pairs • 4 voltages (1.8V/2.5V/3.3V/5V) and ground Note: clocks are not sent through these pings, so the ping assignments after CLK1 in the datasheet should be shifted accordingly. For example, P<19> and M<19> are mapped to C19 and C20, instead of D1 and D2.

Interface between ZDOK+ and ASIC • Driver: SN65LVDS1 (outputs of the chip) • 630 Mbps • Receiver: SN65LVDS2 (inputs of the chip) • 400 Mbps • Supply voltage range, VCC: -0.5V to 4V

Simulink Test Model • BPS design environment is installed on sherwin • Transfer the resulting .bit file to dsp and use iMPACT to program IBOB board BPS environment iMPACT (utility of Xilinx ISE)

Clock Source • Change internal/external clock setting in • Sine waves can be used for clocks, but you might need to set the amplitude to be larger Internal clock: 100MHz external clock: from SMA2

Measurement Results 0.8 400 0.75 275 (179) 0.6 300 0.48 Minimum VDD (V) Core power (mW) 0.4 200 0.32 47.8 (122.4) 0.2 100 2.89 (30.1) ( Energy: pJ/bit) 0 0 Clock frequency (MHz) 0 50 100 150 200 250 300

Resources • http://sherwin.ee.ucla.edu/researchwiki/index.php?title=CAD_Tutorials

Preparation for Chip Testing