Energy Optimization of Probabilistic BooleaN Circuits

1. Energy Optimization of Probabilistic BooleaN Circuits Ching-Yi Huang & Yung-Chun Hu & Black 2014/01/20

2. Outline • Introduction • Problem formulation • Verification for PBC • Energy optimization for PBC • Topological • Testability • PO-aware testability • Level-up assignment • Hspice simulation • Future work

3. Introduction Lower Vdd Power per switch Voltage

4. Introduction • Probabilistic operations • OR: ∨p • AND: ∧p • NOT: ¬p • Let probabilistic parameter p= 0.9 A 0.9 F B

5. Problem Formulation Verification • Given • A Probabilistic Boolean Circuit (PBC) • Confidence level α and error rate (ER) • Report • MIN correctness / AVG correctness of the PBC Synthesis • Given • A deterministic circuit • Correctness constraint (MIN correctness/ AVG correctness) • Derive • Energy optimized Probabilistic Boolean Circuit (PBC)

6. Verification Exact method Monte Carlo method Formula-based method AND: f = a×b×(p) + (1-a×b) ×(1-p) OR: = (1-(1-a) ×(1-b))×(p) + (1-a)×(1-b)×(1-p)

7. Verification • Exact Method • Single Pattern • Time consuming • Formula-based method • Single Pattern • Fastest • Error occurs in fanout-reconvergent circuit • Monte Carlo method • Approximate correctness • Obtain circuit correctness

8. Probabilistic gate assignment • Topological • Balanced topological • Testability • PO-aware testability • Level-up assignment

9. Topological 1 7 2 10 3 8 11 4 5 9 6 Order: 1, 2, 7, 3, 4, 8, 10, 5, 6, 9, 11

10. Balanced topological 1 7 2 10 3 8 11 4 5 9 6 Order: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11

11. Experimental result Under same correctness constrain, voltage = 0.8V

12. Testability N6 E N5 F1 F 0.5 1 N3 A F2 1 N1 B C 0.5 N4 N2 F3 A 1 0.25 D Order: N2, N1, N6, N3, N4, N5

13. PO-aware testability • In PBC, an error effect propagated to one PO is different from an error effect propagated to multi POs. • Evaluation Matrix Let be the weight of , be the testability to PO-aware testability

14. PO-aware testability N6 E N5 F1(w=1) F 0.167 0.33 N3 A F2(w=1) 0.33 N1 B C 0.25 N4 N2 F3(w=1) A 0.33 D 0.083 Order: N2, N6, N1, N3, N4, N5

15. Experimental result

16. Level-up assignment • Observation 0.8 0.8 0.8 1.1 Power = 2.288e-06 About 5 times 0.8 0.9 1.0 1.1 Power = 4.629e-07

17. Level-up assignment Ensure voltage difference 0.1 PI 0.8 0.9 PO 1.0 1.1

18. Look-up table • Predict the correctness suffering and power reduction • Multi-probability assignment • Average correctness suffering per pgate = Monte Carlo sim times = 5 P=0.97, testability<0.2

19. Look-up table Average correctness

20. Look-up table Minimum correctness

21. Hspice simulation • Pseudo random input patterns (LFSR) LFSR type Seed (>0) input Voltage Bit rate Example : [4, 3]

22. Hspice simulation • Waveform

23. Hspice simulation • Dynamic bit rate and simulation duration • Power evaluation methodology in hspice • Power waveform =0

24. Power v.s. IV

25. Hspice simulation • Simulation time is way too long • #gate = 3000, time > 24 hrs • Power component • Dynamic power • Leakage power (constant) • Predict power when frequency is high • Pf=100= + • Pf=200= + Solveand • Then, P2000= +

26. Future work • Hspicesimulation • Paper writing