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Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits

Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits. Ching -Yi Huang & Yung-Chun Hu & Black 2013/12/23. Outline. Introduction Problem formulation Previous works & improvement Experimental results Cell characterization by HSPICE Experimental results

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Timing-aware Energy/Correctness Optimization for Probabilistic BooleaN Circuits

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  1. Timing-aware Energy/Correctness Optimization forProbabilistic BooleaN Circuits Ching-Yi Huang & Yung-Chun Hu & Black 2013/12/23

  2. Outline • Introduction • Problem formulation • Previous works & improvement • Experimental results • Cell characterization by HSPICE • Experimental results • Strategies of probability assignment • Experimental results • Future work

  3. Introduction (1/3) Noise effect Lower VDD

  4. Introduction (2/3) • Probabilistic operations • OR: ∨p • AND: ∧p • NOT: ¬p • Let probabilistic parameter p= 0.9 A 0.9 F B

  5. Introduction (3/3) Energy per switching: Energy ratio p

  6. Problem Formulation Synthesis • Given • A deterministic circuit (every p=1) • Correctness constraint (MIN correctness/ AVG correctness) • Derive • Energy optimized Probabilistic Boolean Circuit (PBC) w/o circuit delay suffering Verification • Given • A deterministic circuit (every p=1) • A PBC which is synthesized from the given deterministic circuit • Confidence level α and error rate (ER) • Report • MIN correctness / AVG correctness of the PBC

  7. Previous Works Exact method Monte Carlo method Formula-based method AND: f = a×b×(p) + (1-a×b) ×(1-p) OR: = (1-(1-a) ×(1-b))×(p) + (1-a)×(1-b)×(1-p)

  8. Comparison between Current & Previous Work Black’s C.-Y.’s Real random

  9. Experimental Results P=0.9, |Pgate| = 50%

  10. Experimental Results P=0.9, |Pgate| = 50%

  11. Experimental Results P=0.9, |Pgate| = 50%

  12. Outline • Introduction • Problem formulation • Previous works & improvement • Experimental results • Cell characterization by HSPICE • Experimental results • Strategies of probability assignment • Experimental results • Future work

  13. Cell Characterization Vdd1 =0.9 Vdd2 = 0.9 Vdd3=1.1 PTM INV 45 nm Wp=630n Lp= 50n Wn=415n Lp= 50n C = 5 fF V=0.9 V=0.9 PI = 1.1 PI/p=1 0.98 1 0.98

  14. Experimental Results • Delay Vdd1 =0.9 Vdd1 =0.9 Vdd1 =0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd3=1.1 Vdd3=1.1 Vdd3=1.1 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 PI = 1.1 PI = 1.1 PI = 1.1

  15. Experimental Results T of falling T of rising T of AVG • Delay Vdd1 =0.9 Vdd1 =0.9 Vdd1 =0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd3=1.1 Vdd3=1.1 Vdd3=1.1 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 PI = 1.1 PI = 1.1 PI = 1.1

  16. Experimental Results • Leakage power Vdd1 =0.9 Vdd1 =0.9 Vdd1 =0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd2 = 0.9 Vdd3=1.1 Vdd3=1.1 Vdd3=1.1 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 V=0.9 PI = 1.1 PI = 1.1 PI = 1.1

  17. Experimental Results • AVG power Vdd1 =0.9 Vdd2 = 0.9 Vdd3=1.1 V=0.9 V=0.9 PI = 1.1

  18. Experimental Results • AVG power with different Cload Larger Cload Smaller Cload

  19. Experimental Results • AVG power with different frequencies & Cload f 4f

  20. Conclusion of AVG Power • Select larger voltages • Larger output loading & high frequency will be a normal situation • Conclusion: • Don’t worry about ! • Ignore this type • Others • Separately calculate • Leakage power = Σ PL • Dynamic energy = Σ 0.5CV2 Vdd1 =0.9 Vdd2 = 0.9 Vdd3=1.1 V=0.9 V=0.9 PI = 1.1

  21. The Influence of Output Loading • Delay • Build up lookup table (by HSPICE simulation) • Calculate by linear interpolation • Leakage power • Build up lookup table (by HSPICE simulation) • Calculate by linear interpolation • Dynamic energy • Directly calculate • NAND gate does too • Ignore the influence by input slew

  22. Evaluation Methods • PBC delay • Topologically estimate • Leakage power of PBC • Σ PL • Dynamic energy of PBC • Σ 0.5CV2

  23. Outline • Introduction • Problem formulation • Previous works & improvement • Experimental results • Cell characterization by HSPICE • Experimental results • Strategies of probability assignment • Experimental results • Future work

  24. Previous Works • Strategies of correctness optimization Random assignment testability-based assignment

  25. Relationship between Voltage and Probability p p Vdd (V) Sd=0.22, max_p = 0.9911 Sd=0.20, max_p = 0.9951 Vdd (V) V:1.100000 INV:p= 0.995129 NAND:p= 0.996492 V:1.000000 INV:p= 0.992174 NAND:p= 0.993130 V:0.900000 INV:p= 0.986867 NAND:p= 0.987055 V:0.800000 INV:p= 0.977118 NAND:p= 0.976586 V:1.100000 INV:p= 0.991110 NAND:p= 0.993031 V:1.000000 INV:p= 0.986408 NAND:p= 0.987629 V:0.900000 INV:p= 0.978538 NAND:p= 0.978756 V:0.800000 INV:p= 0.965342 NAND:p= 0.964777

  26. Strategies • sd = 0.20 • 1.0v vs. 0.9v vs. 0.8v • Topological order • Original vs. timing-aware • Topological order • Topological order vs. traditional testability-based order vs. PO-aware testability-based order • MIN correctness bound vs. AVG correctness bound • Corr = 90%

  27. Experimental Results • C1355; v=1.0

  28. Experimental Results • C1355; v=1.0

  29. Experimental Results • C1355; v=0.9

  30. Experimental Results • C1355; v=0.8

  31. Experimental Results • Circuit size

  32. Experimental Results • 1.0v vs. 0.9v vs. 0.8v (MIN corr. bound = 90%)

  33. Experimental Results • 1.0v vs. 0.9v vs. 0.8v (AVG corr.bound = 90%)

  34. Experimental Results • Original vs. Timing-aware • MIN corr. bound = 90% ; V = 0.9v Ta. Corr. 96% Ta. Corr. 99%

  35. Experimental Results • Original vs. Timing-aware • AVG corr. bound = 90% ; V = 0.9v

  36. Traditional Testability-based Order vs. PO-aware Testability-based Order • No PO information

  37. Experimental Results • Topological order vs. traditional testability-based order vs. PO-aware testability-based order • MIN corr. bound = 90% ; V = 0.9v

  38. Experimental Results • Topological order vs. traditional testability-based order vs. PO-aware testability-based order • MIN corr. bound = 90% ; V = 0.9v ; timing-aware

  39. Experimental Results • Topological order vs. PO-aware testability-based order • AVG corr. bound = 90% ; V = 0.9v

  40. Experimental Results • Topological order vs. PO-aware testability-based order • AVG corr. bound = 90% ; V = 0.9v ; timing-aware

  41. MIN & AVG Correctness

  42. Future work • The heuristic method when assigning mixed probabilities • Find out the reason why topological order is better than testability order

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