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Correlator Testbed: Samuel Tun FASR Subsystem Evaluation

This project involves testing a digital FX correlator in the 1-9 GHz band via a subsystem testbed at 1 GS/s from each antenna. The correlation is conducted offline using FOCIS software by Z. Liu of the CASPER Group. The system uses Xilinx Virtex FPGAs.

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Correlator Testbed: Samuel Tun FASR Subsystem Evaluation

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  1. Digital FX correlator Samuel Tun

  2. FASR Subsystem Testbed (FST) 1-9 GHz in 500 MHz band recorded at 1 GS/s from each antenna. Correlation carried out offline via FOCIS (Z. Liu)

  3. CASPER Group Software and Hardware ROACH I IBOB • Xilinx Virtex 5 SX95T FPGA • - 244 36-kbit BlockRAMs • - 4x CX4 10Gbps connectors - Xilinx Virtex-II Pro 2VP50 FPGA - 232 18-kbit BlockRAMs - 2x CX4 10Gbps connectors

  4. Current Design: f-engine on ROACH

  5. Current Design: f-engine on ROACH (cont.)

  6. Current Design: x-engine on IBOB

  7. ROACH II

  8. ROACH II ROACH I • Xilinx Virtex 6 SX475T FPGA • - 7640 Kb max distributed memory • - 1064 36-kb BlockRAMs • - Up to 8 CX4 10Gbps connectors • Xilinx Virtex 5 SX95T FPGA • - 1520 Kb max distributed memory • - 244 36-kb BlockRAMs • - 4 CX4 10Gbps connectors

  9. Salient Issues • Time delay implementation, including synchronized input from tables to register, fine delay implementation, and input flow disruptions • Power/power2 synchronization to FFT output, or where to put RFI excision logic. • Design on Fabric issues should not exist on ROACH II, although design optimization will be a goal of my visit to the CASPER group.

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