simulator development based on cache architectural level power analysis n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Simulator development based on cache & architectural-level power analysis PowerPoint Presentation
Download Presentation
Simulator development based on cache & architectural-level power analysis

Loading in 2 Seconds...

play fullscreen
1 / 13

Simulator development based on cache & architectural-level power analysis - PowerPoint PPT Presentation


  • 134 Views
  • Uploaded on

Simulator development based on cache & architectural-level power analysis. Presenter: Jun Shen & Yi-hsin Tseng Date: Dec. 4 th , 2007. Agenda. Introduction Analyze cache power consumption & simulation time on different cache properties

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Simulator development based on cache & architectural-level power analysis' - levana


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
simulator development based on cache architectural level power analysis

Simulator development based on cache & architectural-level power analysis

Presenter: Jun Shen & Yi-hsin Tseng

Date: Dec. 4th, 2007

agenda
Agenda
  • Introduction
  • Analyze cache power consumption & simulation time on different cache properties
  • Analyze block buffer’s influence on performance & power consumption
  • Conclusion
  • Q & A
introduction
Introduction
  • Most research in computer architecture focus on performance.
  • “Power” has become an important issue, especially in embedded system.
  • Caches are a great factor to reduce processor and memory speed gap
    • Cache power consumption
      • 27% Intel SA-110 low-power microprocessor
      • 25% of total power in Alpha
      • 43% of total in ARM SA1100
problem
Problem
  • Problem:
    • How do caches affect power consumption & simulation time in whole system?
    • What’s the critical factor of cache power consumption?
    • What’s block buffer’s influence on performance & power consumption?
    • Compare and analyze collected data.
approach 1
Approach 1
  • Using different cache parameters to see the influence on
    • dynamic power consumption (on cache and total)
    • total simulation time in cycles
  • Compare results generated, identify the critical parameter for power reduction
  • Use SimpleScalar & sim-wattch to simulate
    • System Environment: Linux 2.6.20
    • Benchmark: 181.mcf (SPEC CPU2000 Version.1.6.I)
    • Baseline: cache size 128Bytes, 32B cache block size, 4-way associativity, LRU
    • Factors: associativity, page replacement policy, block size, cache size
    • Associativity: 2-way, 4-way, 8-way
    • page replacement policy: LRU, FIFO, random
    • block size: 8Byte, 16Byte, 32Byte, 64Byte
    • Cache size: 2KB, 4KB, 8KB, 16KB
simulation result power consumption
Simulation Result – power consumption

Baseline: Total power consumption: 73.7882 (W)

simulation result average power usage of l1 d cache
Simulation Result – average power usage of L1 D-cache

Baseline: Average power usage of L1 D-cache: 6.0849 (avg_dcache_power)

block buffer experiment
Block Buffer Experiment
  • Study how cache affects the power consumption and performance
    • add simple block buffer above L1 I-Cache
    • Observe the change of power consumption and performance
simulation details
Simulation Details
  • Based on Wattch & Simplescalar
    • If block buffer entry hits, no need to access L1 I-cache,
    • Block buffer is so simple that addr decoder is no longer needed
    • Use set & tag to identify a unique cache block, avoiding duplicate
    • Adopt LRU replacement policy
    • Use sequential searching
conclusion
Conclusion
  • Critical factor of cache power consumption
    • Cache size
    • Block size also plays a role
  • block buffer
    • decrease the average L1 cache power consumption & miss rate
    • increase total execution time
slide12
Q & A

Thank you!

Questions?

reference
Reference
  • [1] G. Albera and I. Bahar. Power and performance tradeoffs using various cache configurations. In Power DrivenMicroarchitecture Workshop at ISCA98, Barcelona, Spain, June 1998.
  • [2] J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE JSSC, 31(11):1703–1714, November 1996.
  • [3] Todd Austin SimpleScalar LLC, Doug Burger Computer Sciences Department University of Wisconsin-Madison, SimpleScalar Tutorial (for tool set release 2.0).