Preliminary Design Review

1. LART-CS08(Train Spotting) Preliminary Design Review February 11, 2008 ECE 492 – Spring 2008

2. MasterPC System Block Diagram RS-232 Station1 PIC Station2 PIC Station3 PIC Station4 PIC Station5 PIC Sensors Sensors Sensors Sensors Sensors Rails & Coils Rails & Coils Rails & Coils Rails & Coils Rails & Coils

3. System Block Diagram • MasterPC communicates to each station via RS-232 • This communication is done in parallel via the Octopus. • PICs at each station will then process this information and send necessary commands to Rails & Switches • Whenever a sensor is triggered, an interrupt will be created that sends information back to the MasterPC

4. Acceptance Test Plan • Test to meet the integrated system requirements for: • Powering and switching • Operation at 16 speed levels • The correct sensor operation • RoHS compliance, EMI/EMC and hazmat requirements • Documenting expandability and adaptability • Test plan will be divided into individual test plans for GUI, networking and the power system

5. System Requirements

6. System Requirements

7. System Requirements

8. Risk Assessment • High risk subsystems • RS-232 communication (PC to PIC) • Digital to PWM on PIC • API • Lower risk subsystems • GUI • Automatic control software • Hardware that resides on the end of the system • Low level hardware to power circuits/rails • Switch control hardware • Sensor hardware

9. Cost Analysis • Direct Costs: Octopus-550, PICs, PCBs, logic chips, serial cables, surge protector. • Total direct costs: $348.70 • Indirect Costs: Labor (2250 Hours), computers, wires, resistors, capacitors. • Total indirect costs: $34,505.00 • Total Costs for project: $34,853.70

10. Work Breakdown Structure

11. Block Diagram: UI Control Automatic Control Manual Control

12. Block Diagram: UI Control

13. Block Diagram: UI Control

14. Block Diagram: Networking Sub-System Block Diagram RS-232 PIC Microcontroller Power & Speed Direction Interrupts PWM Hardware Coils Sensors

15. Block Diagram: Networking PIC Functionality SPECS • Sensors generate interrupts that send data automatically to PC • Rails are powered via PWM. • PWM is generated via secondary PIC • PIC keeps a timer for direction control to supply enough energy to coils. Implements watch-dog to keep voltage < 50ms

16. Block Diagram: Networking PC-to-PIC Frame Format 1-byte Addresses 4-bit Rail Speed 1-bit Switch Info Destination Address Source Address R 15 R 14 R 13 R 12 R 3 R 2 R 1 R 0 S7 S6 S5 S4 S3 S2 S1 S0 8bytes 11bytes 1byte 1byte 1byte

17. PC-to-PIC Communication Specs Block Diagram: Networking RS-232 Standards Destination and Source Addresses 4-bit Data/Rail 1-bit Data/Direction Speed of RS-232 shall be chosen to optimize speed & error

18. Block Diagram: Networking PIC-to-PC Frame Format 1-byte Addresses 1-bit Sensor Info Destination Address Source Address S 7 S 6 S 5 S 4 S 3 S 2 S 1 S 0 3bytes 1byte 1byte 1byte

19. PIC-to-PC Communication Specs Block Diagram: Networking RS-232 Standards Destination and Source Addresses 1-bit Data/Sensor Speed of RS-232 shall be chosen to optimize speed & error

20. Block Diagram: Low Level Mains 120V AC Computer UI/Controller Surge protector/ regulator Computer Microchip/ Router Station Microchip A/C D/C Converter Amplifiers sensors switches rails

21. Block Diagram: Low Level Station Microchip Amplifier switches rails sensors

22. Ethics Analysis • Political Concerns • Environmental • RoHS compliant • avoiding pollution • Funding

23. Ethics Analysis • Social Concerns • Safety • Signs, doors, platforms • Cost • Transportation • Disturbances • Construction, use of land • Opportunities • Jobs

24. Train Spotting QUESTIONS?

25. Test Plans: UI • There will be testing on the following: • Packet Builder • Packet Decoder • Manual Control • Automatic Control

26. Test Plans: Networking • There will be testing on the following: • RS-232 Communication • Sensor Interrupts • Rail Control • Switch Control

27. Test Plans: Low Level • The low level hardware’s three main parts will each be tested individually • The reed switches / proximity sensors • The switching mechanism • Train Speed

28. Requirements Analysis: UI

29. Risk Assessment: UI • Functional Description • The function of the software is to control the system. It includes a user interface, an auto/manual control and failsafe module, a packet builder module, and a packet decoder module. • As a whole the software has a fairly high risk • The user interface is at low risk • The auto/manual control and failsafe is at high risk • The packet builder is at high risk • The packet decoder is at high risk

30. Cost Analysis: UI • Direct Costs: Octopus-550. Total direct costs: $115.00 • Indirect Costs: Labor (750 Hours), computers (8). Total indirect costs: $19,500.00 • Total Costs for project: $19,615.00

31. Requirements Analysis: Networking

32. Risk Assessment: Networking RS-232 Communication This is the communication from the computer to the 5 stations. We have devised a crude packet structure for the data. This subsystem is the structure of the packet and the retrieval of these packets by the PIC controller. If the RS-232 does not work we need to find a different method of data transmission. This would mean redesigning logic inside the PIC and possibly needing completely different hardware. It would delay the low level hardware progress as well as the software development. Risk Factor: P+C – (P*C) = 0.2167 + .4 – (0.2167 * 0.4) = 0.53 high risk Sensor Interrupts This subsystem will monitor the sensors and send a packet of information back to the PC when a sensor has been tripped. We will generate an interrupt in the PIC when this event occurs to make sure the data is sent and sensor information is not missed. This subsystem will be software written in the PIC. Risk Factor: P+C – (P*C) = 0.6 + .4333 – (0.6 * 0.4333) = 0.7733 high risk Rail Control The 4 bit data per rail will be converted into usable analog values for lower level hardware. The 4 bit data is a 16 value range from 0 (rail off) to F (full speed). A second PIC will convert this digital data to a PWM signal for use on the rails. Risk Factor: P+C – (P*C) = 0.5 + .5667 – (0.5 * 0.5667) = 0.7834 high risk Switch Control Signals will be sent out on parallel lines to appropriate low level hardware that will send power to the individual coils. There will be checks to make sure they coils are not over powered or oppositely powered. This subsystem will be software written for the PIC chip. Risk Factor: P+C – (P*C) = 0.5 + .5667 – (0.5 * 0.5667) = 0.7834 high risk

33. Cost Analysis: Networking • Direct Costs: PICs (5), serial cables. Total direct costs: $69.70 • Indirect Costs: Labor (750 Hours). Total indirect costs: $7,500.00 • Total Costs for project: $7,569.70

34. Requirements Analysis: Low Level

35. Risk Analysis: Low Level -Four Tasks: Overall Power, Rail Power, Rail Switching, Sensors -Overall Power: Risk factor of 0.400 (Medium Risk) -Rail Power: Risk Factor of 0.578 (High Risk) -Rail Switching: Risk Factor of 0.337 (Medium Risk) -Sensors: Risk Factor of 0.490 (Medium Risk) Most of the risk in each item is attributed to the high cost of failure. If any item fails, the entire system will not meet the requirements. The additional risk associated with rail power is due to the added complexity of using the DAC chip

36. Cost Analysis: Low Level • Direct Costs: PCBs (7), logic chips (28), surge protector. Total direct costs: $164.00 • Indirect Costs: Labor (750 Hours), wires, resistors, capacitors. Total indirect costs: $7,505.00 • Total Costs for project: $7,669.00