Wafer Level Reliability. System Assembly. PC Board Assembly. End-Use Customer. Component Manufacturing. Raw Material Supplier (i.e. Leadframe). FSC Worldwide Quality & Reliability Built-In Reliability Initiative. Control Points for Emphasis Development Manufacturing.
FSC Worldwide Quality & ReliabilityBuilt-In Reliability Initiative
Failure Mechanism Driven Reliability Characterization
1. DEFINE WORST
2. DEFINE QUALITY
6. DEFINE STRESS
PKG / PROCESS
10. ALR / WLR
11. FINALIZE POR
(Process of Record)
* Note: enter data inputs into appropriate grey shaded fields
Device failures due to built-in defects. WLR stress can help to determine the root cause. The WLR stress: such as PIC, Dielectric BV, Qbd test
Provide the reliability data to designer
through the reliability calculator.
Hot Carrier, Mobile ion, TDDB, EM
Updated on an ongoing basis
Assess reliability risk for new designs and
update the reliability design rules:
Design needs to increase operating
voltage in gate oxide, current density in
metal, and operating voltage on caps
(such as HV poly sink caps).
How to screen out the defect for gate
oxide extrinsic failure.
Consulting available upon request
Develop AC hot carrier stress Methodology
Confirm Berkeley Model for HC
degradation in AC application.
Linear Voltage Ramp
Effect of Mobile Ion under an Applied Field
1. Initial threshold voltage is measured. Vt#1
2. Stress #1: NMOS a negative bias is applied. PMOS a positive bias is applied.
3. Vt#2 is measured.
4. Delta Vt between Vt#1 and Vt#2
5. Stress #2: NMOS a positive bias is applied. PMOS a negative bias is applied.
6. Final threshold voltage is measured. Vt#3
7. Delta Vt between Vt#2 and Vt#3.