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Hierarchical Approaches to T est G eneration and F ault S imulation

This tutorial explores the use of hierarchical approaches in test generation and fault simulation for digital systems with increasing complexities. It discusses defect-oriented testing, high-level modeling, and the use of decision diagrams for hierarchical defect modeling. The tutorial also covers test generation for register-transfer level (RTL) and microprocessor systems, as well as an overview of tools developed at D&T Laboratory.

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Hierarchical Approaches to T est G eneration and F ault S imulation

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  1. Hierarchical Approaches to Test Generation and Fault Simulation REASON Tutorial, MIXDES, Szczecin, Poland June 25, 2004 Raimund Ubar Tallinn Technical University D&T Laboratory Estonia

  2. Abstract • How toimprove the testing quality at increasing complexities of today's systems? • Two main trends: defect-oriented test and high-level modelling • Both are caused by the increasing complexities of systems based on deep-submicron technologies • The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA)or behavioral levels • To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used • Trends to high-level modelling and defect-orientation are opposite • As a promising compromise and solution is:to combine hierarchical approach with defect orientation • Decision Diagrams serve as a good tool forhierarchical modelling of defects in digital systems

  3. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • Decision Diagrams - beyond BDDs • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

  4. Introduction: the Problem is Money? How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Cost of quality Cost Cost of testing 100% Test coverage function Cost of the fault Time Conclusion: “The problem of testing can only be contained not solved” T.Williams Quality Optimum test / quality 0% 100%

  5. Introduction All life is an experiment. The more experiments you make, the better (American Wisdom) Paradox 1: Digital world is finite, analog world is infinite. However, the complexity problem was introduced by Digital World Paradox 2: If I can show that the system works, then it should be not faulty. But, what does it mean: it works? 32-bit accumulator has 264 functions which all should work. So, you should test all the 264 functions! Stimuli Response Y System X Digital case (“continuous”) Y Analog case (samples) X

  6. Introduction: How Much to Test? Time can be your best friend or your worst enemy (Ray Charles) Paradox: 264 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 265 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Y = F(x1, x2, x3) Bridging fault State q 0 y x1 & 1 & x2 * x3 1 Y = F(x1, x2, x3,q)

  7. Introduction: Hierarchy The best place to start is with a good title. Then build a song around it. (Wisdom of country music) Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? Sea of gates & Sequence of 216 bits 16 bit counter 1 System

  8. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • Decision Diagrams (beyond BDDs) • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

  9. Complexity vs. Quality Problems: • Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importancebecause of the complexityreasons • Traditional Stuck-at Fault (SAF) model does not quarantee the qualityfor deep-submicron technologies New solutions: • The complexity can bereduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels • But this moves us even more away from the real life of defects (!) • To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used • But, this is increasing even more the complexity (!) • To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

  10. Fault and defect modeling Defects, errors and faults • An instance of an incorrect operation of the system being tested is referred to as an error • The causes of the observed errors may be design errors or physical faults -defects • Physical faults do not allow a direct mathematical treatment of testing and diagnosis • The solution is to deal with fault models System Defect Component Fault Error

  11. Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open NewState Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

  12. Mapping Transistor Faults to Logic Level A transistor fault causes a change in a logic function not representable by SAF model Function: y Faulty function: x1 x4 Short 0 – defect d is missing 1 – defect d is present d= Defect variable: x2 Generic function with defect: x5 x3 Mapping the physical defect onto the logic level by solving the equation:

  13. Mapping Transistor Faults to Logic Level Function: Faulty function: Generic function with defect: y x1 x4 Short Test calculation by Boolean derivative: x2 x5 x3

  14. Why Boolean Derivatives? Given: Distinguishing function: BD-based approach: Using the properties of BDs, the procedure of solving the equation becomes easier

  15. Functional Fault vs. Stuck-at Fault Full 100% Stuck-at-Fault-Test is not able to detect the short:  Functional fault The full SAF test is not covering any of the patterns able to detect the given transistor defect

  16. Defect coverage for 100% Stuck-at Test Results: • the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) • the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

  17. Generalization: Functional Fault Model Fault-free Faulty Constraints calculation: d = 1, if the defect is present Component with defect: Constraints: Component F(x1,x2,…,xn) y Wd Defect Fault model: (dy,Wd), (dy,{Wkd}) Logical constraints

  18. Functional Fault Model Examples Constraints: Component with defect: Component F(x1,x2,…,xn) y Wd Constraints examples: Defect Logical constraints FF model: (dy,Wd), (dy,{Wkd})

  19. Functional Fault Model for Stuck-ON NOR gate Stuck-on VDD x1 RN x2 Y x1 x2 RP VSS Condition of the fault potential detecting: Conducting path for “10”

  20. Functional Fault Model for Stuck-Open NOR gate Test sequence is needed: 00,10 Stuck-off (open) tx1 x2 y 1 0 0 1 2 1 0 1 VDD x1 x2 Y x1 x2 VSS No conducting path from VDD to VSS for “10”

  21. Functional Fault Model x*k xk d Example: Bridging faultbetween leadsxkandxl The conditionmeans that in order to detect the short between leadsxkand xl on the leadxk we have to assign toxkthe value 1 and toxlthe value 0. xl xk*= f(xk,xl,d) Wired-AND model

  22. Functional Fault Model Bridging fault causes a feedback loop: Example: A short between leads xkand xlchanges the combinational circuit into sequential one x1 y & x2 & x3 Equivalent faulty circuit: x1 y & & x2 x3 tx1 x2 x3 y 1 0 1 0 2 1 1 1 1 Sequential constraints: &

  23. Mapping High level k WFk Component Low level WSk Bridging fault Environment Mapping First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System

  24. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • Decision Diagrams (beyond BDDs) • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

  25. Register Level Fault Models RTL statement: K: (If T,C) RD F(RS1, RS2, … RSm),  N Components (variables) of the statement: RT level faults: K  K’ - label faults T  T’ - timing faults C  C’ - logical condition faults RD RD - register decoding faults RS RS - data storage faults F  F’ - operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults K - label T - timing condition C - logical condition RD - destination register RS - source register F - operation (microoperation)  - data transfer  N - jump to the next statement

  26. Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer (n inputs log2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

  27. Fault models and Tests Functional fault model Dedicated functional fault model for multiplexer: • stuck-at-0 (1) on inputs, • another input (instead of, additional) • value, followed by its complement • value, followed by its complement on a line whose address differs in one bit Test description

  28. Faults and Test Generation Hierarchy Functional Structural Higher Level Module approach approach ki k Component Lower level WFki S Test F W k WFk WSki System Network Bridging fault F W of modules k Environment S Test W F k ki Interpretation of WFk: - asa test on the lower level - asa functional fault on the higher level Module Network F W ki of gates d W Test F ki ki Circuit e Gat

  29. Hierarchical Defect-Oriented Test Analysis BDDs DDs

  30. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • Decision Diagrams (beyond BDDs) • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

  31. Binary Decision Diagrams y 1 Functional BDD x1 1 0 x2 x3 Simulation: x4 x5 01 1 0 1 0 0 Boolean derivative: x6 x7 0

  32. Elementary Binary Decision Diagrams Elementary BDDs: AND x1 x1 x2 x1 x2 x3 y & x2 y x3 + Adder x3 x1 OR x2 x1 y 1 y x1 x2 x3 x3 x2 x2 x3 x3 NOR x1 x2 y x1 x2 x3 1 x3

  33. Building a SSBDD for a Circuit Structurally Synthesized BDDs: DD-library: y a b Given circuit: x1 x1 x22 a a b x21 1 x2 y x21 x3 & x22 1 SSBDD x3 Superposition of DDs b y x22 x22 a y x1 Compare to x3 x3 Superposition of Boolean functions: x21 b a

  34. Macro 1 y & d 2 73 6 & 71 a 1 & e 3 72 7 b 4 5 1 y & 5 73 c 6 71 72 2 0 & & & Representing by SSBDD a Circuit Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds y = cyey = cyey = x6,e,yx73,e,y deybey y = x6x73  ( x1  x2 x71) ( x5 x72)

  35. Macro 1 & d 2 & 71 a & e 3 72 7 b 4 y & 5 73 c 6 & & & Fault modeling on SSBDDs The nodes represent signal paths through gates Two possible faults of a DD-node represent all the stuck-at faultsalong the signal path y 73 6 1 5 1 71 72 2 123 4 5 6 7 y 1 1 0 0 1 1 0 Test pattern:

  36. High-Level Decision Diagrams R Superposition of High-Level DDs: A single DD for a subcircuit 2 0 y # 0 4 1 R 2 M1 0 0 2 y y R + R 3 1 1 2 R2 1 IN + R 2 1 IN 2 R 1 3 0 y R * R 2 R2 +M3 1 2 1 IN* R 2 M2 Instead of simulating all the components in the circuit, only a single path in the DD should be traced

  37. Data Path M A ADR B C z 1 MUX 1 z CC z 2 MUX 2 y x CON D Control Path d l / ¢ q q FF High-Level Decision Diagrams A digital system: System is partitioned into 4 subcircuits, each represented by a DD

  38. High-Level Vector Decision Diagrams A system of 4 DDs Vector DD 0 A 0 0 C ¢ B’ + C’ q M=A.B.C.q i ¢ q x A’ + B’ ¢ ¢ q B + C i A B q #1 1 0 #5 x  ¢ A + 1 A 1 0 A 1 C  x A’ + 1 i 3 1 A  i C’ q x q  ¢ ¢ C + B C #4 #3 4 0 0 1 B x x ¢ ¢ ¢ A + B + C C A B’ + C’ 0 0 A i q x x A’ + B’+C’ i A C 1 1 B #2 2 x ¢ ¢ ¢ B + C q B  B’ A q 4 0 #5 3 0 C 0 x  ¢ B A’ + B’ x ¢ q # A q 1 i B C q  B’ i 2 0 1 0 #5 q x ¢ x # q ¢ ¢ 4 A + B C B A #5 1 A 1  B’ + C’ 1 3 i 0 1 C q x # 2  C’ i C #5 q 4 0 2 4 1 #5 x # 5 x B  ¢ C A 1 3,4 # 3

  39. Fault Modeling on High Level DDs • Terminal nodesrepresent: • RTL-statement faults: • data storage, • data transfer, • data manipulation faults High-level DDs (RT-level): • Nonterminal nodes represent: • RTL-statement faults: • label, • timing condition, • logical condition, register decoding, • operation decoding, • control faults

  40. Hierarchical Diagnostic Modeling High-Level DD-s Boolean differential algebra BDD-s Two trends: • high-level modeling • to cope with complexity • low-level modeling • to cope with physicaldefects,to reach higher acuracy

  41. Outline • Introduction to Digital Test • How to improve test quality at increasing complexity of systems • High-level modelling and defect-orientation • Decision Diagrams (beyond BDDs) • Hierarchical test generation • General concepts • Test generation for RT Level systems • Test generation for Microprocessors • Hierarchical fault simulation • Overview of tools developed at D&T Lab

  42. Hierarchical Test Generation • In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes • These modes will usually contain: • a list of controlsignals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or • a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path • The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) • In the hierarchical approach, top-down and bottom-up strategies can be distinguished

  43. Hierarchical Test Generation Approaches Bottom-up approach: Top-down approach: A A System System a a’ D D’ B B c’ C C c a’,c’,D’ fixed x - free a,c,D fixed x - free a a’x D d’x A = a’x D’ = d’x C = c’x A = ax D: B = bx C = cx c c’x Module Module

  44. Hierarchical Test Generation Approaches A System Bottom-up approach: • Pre-calculated tests for components generated on low-level will be assembled at a higher level • It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing • However, the bottom-up algorithms ignore the incompletenessproblem • The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test • The approach would work well only if the the corresponding testability demands were fulfilled a D B C c a,c,D fixed x - free a D A = ax D: B = bx C = cx c Module

  45. Hierarchical Test Generation Approaches Top-down approach: A System • Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions. • This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules • However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied a’ D’ B c’ C a’,c’,D’ fixed x - free a’x d’x A = a’x D’ = d’x C = c’x c’x Module

  46. R 2 0 y # 0 4 y y y y 1 1 2 3 4 R 2 0 0 a 2 R · c y y R + R 1 3 1 M + 1 2 1 e 1 · IN + R M R 2 3 2 1 b · IN * M · 2 IN · 2 d R 1 3 0 y R * R 2 1 2 1 IN* R 2 Hierarchical Test Generation on DDs Hierarhical test generation with DDs:Scanning test(defect-oriented) Single path activation in a single DD Data function R1* R2is tested Decision Diagram Data path Control: y1 y2 y3 y4 = x032 Data: For all specified pairs of(R1, R2) Test program: Low level test data (constraints W)

  47. y y y y 1 2 3 4 a R · c 1 M + 1 e · M R 3 2 b · * M · 2 IN · d Test Generation on High Level DDs High-level test generation with DDs: Conformity test (High-level faults) Decision Diagram Multiple paths activation in a single DD Control function y3 is tested R 2 0 y # 0 4 Data path 1 R 2 0 0 2 y y R + R 3 1 1 2 1 IN + R 2 1 IN 2 R 1 3 0 y R * R 2 1 2 1 IN* R Control: For D = 0,1,2,3: y1 y2 y3y4 = 00D2 Data: Solution of R1+ R2 IN  R1  R1* R2 Test program: 2 Activating high-level faults:

  48. & & & Gate-level Test Generation • Fault sensitisation: • x7,1= D • Fault propagation: • x2=1, x1=1, b =1, c =1 • Line justification: • x7= D = 0: x3= 1, x4= 1 • b = 1: (already justified) • c = 1: (already justified) Structural gate-level testing: Path activation 1 1 Macro 1 d 1 1 a & 2 & 71 D D D 1 & e 3 7 72 b 1 1 4 y D D & 5 73 c 1 6 Test pattern Symbolic fault modeling: D = 0 - if fault is missing D = 1 - if fault is present

  49. & & & Defect-Oriented Test Generation Component F(x1,x2,…,xn) y Activate a path Test generation for a bridging fault: Bridge between leads 73 and 6 Wd Defect Macro 1 1 d 1 & 2 a & 71 D D • Fault manifestation: • Wd= x6x7= 1: x6=0, x7=1, • x7= D • Fault propagation: • x2=1, x1=1, b =1, c =1 • Line justification: • b = 1: x5= 0 D & e 3 72 7 b 1 4 1 y D D & 5 73 c 1 0 6 Wd

  50. Macro 1 & d 2 & 71 a & e 3 72 7 b 4 y & 5 73 c 6 & & & Test Generation with SSBDDs DefectWd manifestation: Wd= x6x7= 1: x6=0, x7=1, x7= D Functional Fault dx7 propagation: x1=1, x2=1, x5=0 y No fault: dx7 =0: x7=1 73 6 (dx7,Wd) 1 5 1 Bridge between leads 7 and 6:(dx7,Wd) 71 72 2 Test pattern for the node 71 at the constraint Wd= x6x7= 1: Defect: dx7 =1: x7=0 123 4 5 6 7 y 1 10 01 1 0

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