2007 DSD

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# 2007 DSD - PowerPoint PPT Presentation

2007 DSD. Binary Codes. Conversion( 轉換 ) or Coding ( 編碼 ). Do NOT mix up conversion of a decimal number to a binary number with coding a decimal number with a BINARY CODE.  13 10 = 1101 2 (This is conversion)  13 ←→ 0001|0011 (This is coding) Data ( 資料表示法 ) Type of Digitalized Data

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## 2007 DSD

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1. 2007 DSD NTU DSD (Digital System Design) 2007

2. Binary Codes NTU DSD (Digital System Design) 2007

3. Conversion(轉換) or Coding (編碼) • Do NOT mix up conversion of a decimal number to a binary number with coding a decimal number with a BINARY CODE.  • 1310 = 11012 (This is conversion)  • 13 ←→ 0001|0011 (This is coding) Data (資料表示法) • Type of Digitalized Data • Numeric (數值資料) • 可進行加、減、乘、除等算術運算的資料 • Character or Alpha Numeric (文數資料) • 不能拿來運算的資料 • 常見的數值表示法可以分成兩大類 • 整數 • 實數 (分數/浮點數) • 整數與實數最大的差別是 • 實數能夠表示包含小數的數值資料 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

4. Sign-Magnitude Format • Positional representation using n bits • X = Xn Xn-1 Xn-2 … X1 X0 • Sign-magnitude format • Left most bit position (X n) is the sign bit, only bit that is complemented • 0 for positive number • 1 for negative number • Remaining n-1 bits represent the magnitude • Min: -(2n - 1) = 1111 1111 (-127) • Max: +(2n - 1) = 0111 1111 (+127) • Zero: -0 = 1000 0000 • Zero: +0 = 0000 0000 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

5. Ones Complement Format (1的補數) • Negative numbers are represented by a bit-by-bit complementation (對所有bit做補數運算) of the (positive) magnitude (the process of negation) • Sign bit interpreted as in sign-magnitude format • Examples (8-bit words): • +42 = 00101010 • -42 = 11010101 • Min: - (2n - 1) = 1000 0000 (-127) • Max: +(2n - 1) = 0111 1111 (+127) • Zero: - 0 = 1111 1111 (0) • Zero: +0 = 0000 0000 (0) Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

6. Twos Complement Format (2的補數) • Most significant bit is the “sign bit”. • Twos Complement = Ones Complement + 1 • Number representation is not symmetric. (非對稱式表示) • Only one representation for zero. • Easy to negate, add, and subtract numbers. • A little bit trickier for multiply and divide. • Examples (8-bit words): • +42 = 00101010 • -42 = 11010101 (1’s Complement) • -42 = 11010110 (2’s Complement) = 11010101 + 00000001 • Min: - (2n) = 1000 0000 (-128) • Max: +(2n - 1) = 0111 1111 (127) • Zero: = 0000 0000 (0) Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

7. 9 6 6 -6 -9 0 0110 0 1001 1 1010 0 0110 1 1010 + + + + + -9 -9 9 9 9 1 0111 1 1001 0 1001 0 1001 0 1001 Signed 2’s Complement Addition • Add the two numbers, including their sign bit, and discard any carry out of left-most (sign) bit • Examples 3 10 0011 15 0 1111 Overflow -3 1 1101 -18 10 1011 18 1 0010 Overflow Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

8. 9 -9 1 1010 0 1001 + + -9 9 1 1001 0 1001 Detecting 2’s Complement Overflow • When adding two's complement numbers, overflow will only occur if the numbers being added have the same sign but the sign of the result is different • If we perform the addition • Overflow occurs when an-1 = bn-1 but ≠ sn-1 • signs of both operands are the same, and sign of sum is different. 18 1 0010 -18 10 1110 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

9. 3 3 -3 -3 1101 0011 0011 1101 - - - - -2 -2 2 2 0010 1110 1110 0010 3 -3 -3 3 0011 1101 0011 1101 + + + + 2 -2 2 -2 1110 0010 1110 0010 -5 -1 5 1 1111 0001 0101 1011 Signed 2’s Complement Subtraction • To subtract two's complement numbers we first negate the second number and then add the corresponding bits of both numbers. • Examples: Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

10. 0 00001111 Source 00000000 00001111 Destination 00001111 15 00000000 00001111 15 Zero Extension (零擴展) • Assembly • When you copy a smaller value into a larger destination, the MOVZX instruction fills (extends) the upper half of the destination with zeros. • mov bl,00001111b • movzx ax,bl ; zero-extension Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

11. 1+16+32+64=113 01110001 113 10001111 Source 10001110 1’s 10001111 2’s 11111111 10001111 Destination -113 10001111 -113 11111111 10001111 -113 Sign Extension (符號擴展) • Assembly • The MOVSX instruction fills the upper half of the destination with a copy of the source operand's sign bit. • mov bl,10001111b • movsx ax,bl ; sign extension Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

12. 2-1 = 0.5 2-2 = 0.25 2-3 = 0.125 Fractions (分數): Fixed-Point • How can we represent fractions? • Use a “binary point” to separate positive from negative powers of two -- just like “decimal point.” • 2’s complement addition and subtraction still work. • if binary points are aligned 00101000.101 40.625 00000001.010 1.25 1’ Comp 11111110.101 -1.25 + 2’ Comp 11111110.110 -1.25 00100111.011 39.375 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

13. 1b 8b 23b S Exponent Fraction or Mantissa Very Large and Very Small Number • Large values: 6.023 x 1023 • 602,300,000,000,000,000,000,000 • Requires 79 bits • Small values: 6.626 x 10-34 • 0.000,000,000,000,000,000,000,000,000,000,000,662,6 • Requires >110 bits • Use equivalent of “scientific notation”: F x 2E • Need to represent • F or M (fraction 分數/Mantissa浮點數 ) • E (exponent 指數) • Sign (正負號) • IEEE 754 Floating-Point Standard (32-bits): Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

14. Floating Point Number Representation • If x is a real number then its normal form representation is: • x = f • BaseE • Where • f : mantissa • E: exponent • Example: • 125.3210 = 0.12532 • 103 • - 125.3210 = -0.12532 • 103 • 0.054610 = 0.546 • 10–1 • The mantissa is normalized, so the digit after the fractional point is non-zero. (小數點以下的第一位數為非零) • In binary, the leading digit is always 1, so it is normally hidden. • If needed the mantissa should be shifted appropriately to make the first digit (after the fractional point) to be non-zero & the exponent is properly adjusted. Mantissa Exponent Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

15. Normalizing Numbers • 134.1510 = 0.13415 x 103 • 0.002110 = 0.21 x 10-2 • 101.11B = .10111 x 23 or 1.0111 x 22 (hidden1) • 0.011B = .11 x 2-1 or 1.1 x 2-2 (hidden1) Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

16. Excess-3 Code (超三碼) Recall: BCD Code • 010 = 00002 • 110 = 00012 • 210 = 00102 • 310 = 00112 • 410 = 01002 • 510 = 01012 • 610 = 01102 • 710 = 01112 • 810 = 10002 • 910 = 10012 • 1010 = 0001 00002 = 0011Exc-3 = 0100Exc-3 = 0101Exc-3 = 0110Exc-3 = 0111Exc-3 = 1000Exc-3 = 1001Exc-3 = 1010Exc-3 = 1011Exc-3 = 1100Exc-3 互補 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

17. Excess (Biased) Representation (超碼表示法) • Effectively moves the scale • The “all-zeros” means the largest negative number (最大的負數) • The “all-ones” means the largest positive (最大的正數) 8 bit excess-127 representation • 0 representation 0111 1111 • Largest positive 1111 1111 (+128) • Largest negative 0000 0000 (-127) 1111 1111 +128 1111 1110 +127 … 1000 0000 1 0111 1111 0 0111 1110 -1 … 0000 0001 -126 0000 0000 -127 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

18. IEEE Standards for Floating-Point Representation • Single Precision • Double Precision Excess 127 1 8 23 Sign Exponent Mantissa Excess 1023 52 1 11 Sign Exponent Mantissa Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

19. Single Precision IEEE Standards • The sign field for mantissa is 0 for positive or 1 for negative • In the mantissa, the decimal point is assumed to follow the first ‘1’. Since the first digit is always a ‘1’, a hidden bit is used to representing the bit. The fraction is the 23 bits following the first ‘1’. The fraction really represents a 24 bit mantissa. • The exponent field has a bias of 127. Excess 127 1 8 23 Sign Exponent Mantissa Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

20. 100 : One 101 : Ten (Deca / da) 102 : Hundred (Hetco / h) 103 : Thousand (Kilo / k) 106 : Million (Mega / M) 109 : Billion (Giga / G) 1012 : Trillion (Tera / T) 1015 : Quadrillion (Peta / P) 1018 : Quintillion (Exa / E) 1021 : Sextillion (Zetta / Z) 1024 : Septillion (Yotta / Y) 10-1 : Tenth (Deci / d) 10-2 : Hundredth (Centi / c) 10-3 : Thousandth (Milli / m) 10-6 : Millionth (Micro / μ) 10-9 : Billionth (Nano / n) 10-12 : Trillionth (Pico / p) 10-15 : Quadrillionth (Femto / f) 10-18 : Quintillionth (Atto / a) 10-21 : Sextillionth (Zepto / z) 10-24 : Septillionth (Yocto / y) Some Special Numbers Prefix & Symbol Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

21. Quiz Solution 1) Please use 16 bit system & twos complement method perform AC0016 + 123410 – 67408 and please representation the result into Excess-127 Code • AC0016 = 1010 1100 0000 0000 • 123410 = 4D2 = 0000 0100 1101 0010 • 67408 = 110 111 100 000 = 0000 1101 1110 0000= 1111 0010 0001 11111s= 1111 0010 0010 00002s • 1010 1100 0000 0000 + 0000 0100 1101 0010 = 1011 0000 1101 0010 • 1011 0000 1101 0010+ 1111 0010 0010 0000 = 1) 1010 0010 1111 0010 • 1010 0010 1111 0010 + 0000 0000 0111 1111= 1010 0011 0111 0001Excess-127 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

22. Quiz Solution 2) Please extension the results in 1) into 32 bit system and translate it into Decimal • Since 1)’s Solution is 1010 0011 0111 0001Excess-127 • The Real Value is 1010 0011 0111 0001Excess-127 – 0000 0000 0111 1111 = 1010 0010 1111 0010 • Sign Extension to 32-bit System= 1111 1111 1111 1111 1010 0010 1111 0010 • 1111 1111 1111 1111 1010 0010 1111 00102s=> 1111 1111 1111 1111 1010 0010 1111 00011s=> 0000 0000 0000 0000 0101 1101 0000 11102 • 0000 0000 0000 0000 0101 1101 0000 1110 = 23822 • So, answer is -23822 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

23. Quiz Solution 3) Please convert Decimal -0.001234 x 1013 into IEEE Single Precision Binary format • -0.001234 x 1013 = -1.234 x 1010 • 1.234 x 1010 = 1234000000010 = 2DF85750016= 0010 1101 1111 1000 0101 0111 0101 0000 0000 • To Floating Point= 1.0 1101 1111 1000 0101 0111 0101 0000 0000 x 233 • 3310 = 0010 00012 => 0010 0001 + 0111 1111 = 1010 0000Excess-127 • IEEE Single Precision Binary format = 1 10100000 01101111110000101011101= 1101 0000 0011 0111 1110 0001 0101 1101 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

24. Quiz Solution Reference Reference: http://www.h-schmidt.net/FloatApplet/IEEE754.html Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/

25. Quiz Solution 4) Please convert IEEE Single Precision 7EC0000F16 into Decimal format • 7EC0000F16 = 0111 1110 1100 0000 0000 0000 0000 11112= 0 11111101 10000000000000000001111IEEE • 11111101Excess-127 => 1111 1101 – 0111 1111 = 0111 11102 = 12610 • 7EC00000F16 => +1.10000000000000000001111 x 2126(有算至此就給分) • +1.10000000000000000001111 x 2126=> 2126 = 8.5070591730234615865843651857942 x 1037=> 1.10000000000000000001111 = 1 + 1/21 + 1/220 + 1/221 + 1/222 + 1/223 ≒ 1.5 • 1.5 x 8.5070591730234615865843651857942 x 1037≒ 12.760588759535192379876547778691 x 1037≒ 1.27606 x 1038 5)BD660000 => -5.6152344e-2 Jackie Kan - 2007 (jackiekan@LinTon.1D24H.com/jackiekan@csie.ntu.edu.tw) http://linton.1d24h.com/~jackiekan/