PowerMixer IP : IP-Level Power Modeling for Processors

1. PowerMixerIP: IP-Level Power Modeling for Processors Shan-Chien Fang1 Jia-Lu Liao2 Chen-Wei Hsu2Chia-Chien Weng2 Shi-Yu Huang2 Wen-Tsan Hsieh3 Jen-Chieh Yeh3 1TinnoTek Inc, Taiwan (service@tinnotek.com.tw) 2Dept. of Electrical Engineering, National Tsing Hua University, Taiwan 3Industrial Technology Research Institute, Taiwan

2. Introduction • Power dissipation has become a major design metric • IR drop, signal integrity • power budgeting, power tradeoff, battery lifetime • power grid design, thermal analysis, packaging • High-level power estimation • enable power optimization in early stage • achieve higher power saving • fast but often suffer from inadequate accuracy • PowerMixerIP • IP-based power modeling/analysis tool • bottom-up power modeling/analysis methodology • fast and accurate power analysis for large SoC designs

3. Power Modeling Strategies General IP Model • For general IP • Adopt operation-mode-based model • By observing user-defined operation mode and key signals PowerMixerIP Processor Model • Specific for processor • Adopt instruction-level or stage-accurate model • By observing the program counter register and the instruction registers

4. IP-Based Power Simulation μProcessor Cache Bus DMA ASICs …… (1) SoC Netlist (2) IP Power Models (.PMF) PowerMixerIP (IP-Based Power Simulation) (4) Std. Cell Power Library (3) Essential VCD Power Profile PowerMixerIPcan significantly speed up the simulation process!

5. Processor Modeling Example:PAC-DSP Core Architecture • PACDSP core is a VLIW processor with 8 pipeline stages and 5 issues • ISA supports 206 instructions

6. Energy Model Complexity • Enumerate all possible instruction combinations • 206 is total number of instruction • 5 is number of instructions per issue • O(2065) • Divide all instructions into instruction classes • instructions with similar behaviors in one class • divide instructions into 13 types • O(2065)O(135) • Sum up the individual power of each instruction in a issue • O(135)O(13) • Consider power consumption of an instruction in eight different stages • O(13)O(13*8) = O(104)

7. Basic Period of Processor Energy Model • Divide the execution time of training programs into a number of basic periods • Basic period • the time period during which the program counter’s value is not changed • calculate energy Eiof each basic period i CLK PC 10000039 10000040 10000047 1000004e 10000056 E1 E2 E3 E4 E5

8. Generate Energy Matrix • Energy Equation for Each Basic Period • Energy Matrix Ni,1 x J1 + Ni,2 x J2 + …… + Ni,104 x J104 = Ei • Ei: energy consumption of the basic period i • Ni,s: number of times the s-th stage is executed in basic period i • Js : one-time execution energy of the stage s • s : pipeline stage id in each instruction class • Solve the energy matrix to obtain Jvector

9. Experimental Results Accuracy and Runtime Comparisons of IP-level Power Analysis CLK STATUS ENDE Gate-level General IP model AES Power Waveform

10. Power Exploration & Design Trade-Off • Application: H.264 (100K instructions) • Specification: PAC-DSP with various caches @ 240MHz TTarget: Execution time of different cache sizes Treference: Execution time of 32K cache size ETarget: Energy of different cache sizes Ereference: Energy of 32K cache size

11. Summary • PowerMixerIP: IP-based power analysis tool • Construct the power models of processors and other various IPs automatically • Explore potential power-performance trade-offs at an early SoC design stage • ~100X power simulation speedup with high estimation accuracy