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CPU Design Project Synthesis Report

CPU Design Project Synthesis Report. ELEC 7770-001 - Dr. Agrawal Lee W. Lerner April 24, 2007. Outline. Synthesis Goals Synthesis Design Flow Mentor Graphics IC Flow Design Tools Various other software tools used for design debugging and verification Synthesis Results

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CPU Design Project Synthesis Report

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  1. CPU Design ProjectSynthesis Report ELEC 7770-001 - Dr. Agrawal Lee W. Lerner April 24, 2007

  2. Outline • Synthesis Goals • Synthesis Design Flow • Mentor Graphics IC Flow Design Tools • Various other software tools used for design debugging and verification • Synthesis Results • Area and Delay reports • Netlist verification • Conclusions • Suggestions for improvement

  3. Synthesis Goals • Take a verified design modeled in hardware description language (VHDL in our design project) • Generate a gate- level netlist for the circuit that optimizes either: • 1. Area • 2. Delay • 3. Both (to a lesser extent) • Verify functionality of netlists generated • Decide on synthesized netlist to proceed with in project design flow

  4. Synthesis Design Flow • Mentor Graphics IC Design Flow tools used: • Leonardo Spectrum 8 • Synthesize gate-level netlists optimized for area and delay from provided VHDL CPU design • Flextest • Verify that synthesized gate-level netlists compile

  5. Synthesis Design Flow • Leonardo Spectrum 8 V. P. Nelson, Tutorial Documents for Mentor Graphics Tools, http://www.eng.auburn.edu/department/ee/mgc/mentor.html

  6. Synthesis Design Flow • Netlists generated and corresponding reports: • 1. Area Optimization (CPU_areaOpt.edf) • Area report: areaOpt_areaReport • Delay report: areaOpt_delayReport • 1. Delay Optimization (CPU_delayOpt.edf) • Area report: delayOpt_areaReport • Delay report: delayOpt_delayReport

  7. Synthesis Results • areaOpt_areaReport

  8. Synthesis Results • areaOpt_delayReport

  9. Synthesis Results • delayOpt_areaReport

  10. Synthesis Results • delayOpt_delayReport

  11. Synthesis Results • Netlist comparison

  12. Synthesis Results • Synthesis Verication: FlexTest • Netlists compile correctly • Need for DFT (scan design)

  13. Conclusions • Used Leonardo Spectrum 8 to generate gate-level netlists optimized for area and delay independently • Netlists compile correctly • Due to area and delay similarity between generated netlists it was decided that we could proceed with either netlist in the design project

  14. Conclusions • Suggestions for improvement • Improved communication between team members (i.e. weekly status reports/presentations) • Every team member has input at each stage in the design • Identify coding and design errors earlier • Identify need for and implement DFT before synthesis • Improved CPU design in a shorter time

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