A cmos adiabatic logic for low power circuit design
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A CMOS Adiabatic Logic for Low Power Circuit Design. IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)i Aug. 4-5,2004. 所別 : 積體電路設計研究所 指導教授 :林志明 教授 學號 : 95662004 學生:賴秀全. Outline. Abstract Introduction

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A cmos adiabatic logic for low power circuit design

A CMOS Adiabatic Logic for Low Power Circuit Design

IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004)i Aug. 4-5,2004

所別 : 積體電路設計研究所

指導教授 :林志明 教授

學號 : 95662004

學生:賴秀全


Outline
Outline

  • Abstract

  • Introduction

  • Adiabatic circuit of two grades connecting

  • ADL inverter

  • ECRL inverter

  • HEERL inverter

  • Proposed circuit architecture

  • Energy analysis

  • Conclusion


Abstract
Abstract

  • Designed the low power energy recovery circuit using the adiabatic method.

  • Since the circuit operates low frequency (down to 200Mhz), we can save the power consumption than other adiabatic circuit. Proposed circuit was designed usingTSMC0.35um CMOS Technology.

  • Simulation result shows that the circuit can be operating up to 400Mhz


Introduction
Introduction

  • The power dissipation is a very important concern in the performance of VLSI circuits

  • Using the AC power supply can be charge recovery to original power supply, which is an advantage for low power circuit design. We call the method namelyadiabatic logic。Although adiabatic circuits consume zero power theoretically, they show nonzero power consumption due to resistance in switching the transistor.


A cmos adiabatic logic for low power circuit design

Figure1 Adiabatic circuit of two grades connecting




A cmos adiabatic logic for low power circuit design

Figure 4HEERL inverter





Proposed inverter vs ecrl
Proposed inverter VS ECRL

Figure 6 Proposed inverter VS ECRL


Proposed inverter vs heerl
Proposed inverter VS HEERL

Figure 7 Proposed inverter VS HEERL


Power consumption comparison
Power consumption comparison

Figure 8 Power consumption comparison


Conclusion
Conclusion

  • This circuit used a 4-phase trapezoidal power clock for cascading stage.

  • The proposed circuit was designed more simply than HEERL and the power consumption of it can fall by 30% comparing with HEERL under 200Mhz.


References
References

  • W.C Athas, L.J.Svensson, J.G.Koller, N.Tzartzanis, etc. “Low-power digital systems based on adiabatic-switching principles,” lEEE Trans. On VLSl Systems, vol. 2, no.4,December 1994.

  • A.G. Dickinson, J.S. Denker. “Adiabatic dynamic logic,” IEEE J.S.S.C., vol. 30,pp.311-315, March 1995.

  • Chulwoo Kim, Seung-Moon Yoo, Sung-Mo (Steve) Kang, “NMOS energy recover logic,” Electronics Letters, vol. 36, no.16, August 2000.