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Outline

Outline. Overview Specific Objective Design Procedures Summary of GP1 Achievements Background Theory Detailed Design Project Realization Conclusion. Overview. Recently, building low-power VLSI systems is highly in demand

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Outline

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  1. Outline • Overview • Specific Objective • Design Procedures • Summaryof GP1 Achievements • Background Theory • Detailed Design • Project Realization • Conclusion

  2. Overview • Recently, building low-power VLSI systems is highly in demand • Most of the VLSI applications such as digital signal processing, image and video processing and microprocessors use arithmetic operations • CMOS is one of the VLSI electronics that used in microprocessors, microcontrollers, and other digital logic circuits as the full adder

  3. Specific Objective Design and characterize a low-powerCMOS Full adder

  4. Full Adder • A full adder is a combinational circuit that forms the arithmetic sum of three input bits

  5. Design Procedure

  6. Summary of GP1 Achievements

  7. Background Theory

  8. Capacitive Inputs Advantages • Very large fan in capability • Fewer transistors and interconnections resulting in small area consumption • Amount of charging and discharging currents Minority FA Threshold logic FA

  9. Minority Full Adder • A minority gate has three inputs and one output and produces an output value 1 when a minority of input values adders and selection of the low power design are 1

  10. Minority Full Adder 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 This design has rail to rail output signals and works properly at low voltages

  11. Minority Gate Implementation Using Capacitor Using Inverters

  12. Threshold Logic (TLG) Full Adder • Advantages • The total number of components are reduced such as the number of: • Transistors • Capacitors • The output signal is regular and has a large voltage swing

  13. Threshold Logic (TLG) Full Adder It consists of two TLG

  14. (TLG) Implementation Carry Stage Sum Stage

  15. Detailed Design

  16. Wired Inverters Minority FA

  17. Wired Inverters Minority FA

  18. CMOSInverter Voltage Transfer Characteristics • The input low voltage (VIL) and the input high voltage (VIH) are identified in Figure

  19. CMOSInverter Voltage Transfer Characteristics • There are two cases when PMOS and NMOS operate; Case (1): VI is more than VIH PMOS operating in the saturation region NMOS operating in the linear region Drain current for both transistors :

  20. CMOSInverter Voltage Transfer Characteristics • For NMOS transistor VGS = VI and VGS = VO; whereas for PMOS transistor, VGS = VI-VDD and VDS = VO-VDD +

  21. CMOSInverter Voltage Transfer Characteristics Case (2): As VI less than VIL NMOS operating in the saturation region PMOS operating in the linear region

  22. CMOSInverter Voltage Transfer Characteristics To solve for Vo , VI= VIL

  23. Width Design

  24. MIN FA using wired inverters Design Results

  25. MIN FA Using Wired Inverters

  26. Average Currents & Delay

  27. Capacitive Inputs

  28. Capacitive Inputs Full Adders Design

  29. Capacitive Inputs Full Adders Design • Accept multiple inputs signals • Calculates the weighted sum of all input signals • Controls the ON and OFF states of the transistor • The n-MOSFET switching ON or OFF depends on whether is greater than or less than the threshold voltage of the transistor

  30. Capacitive Inputs Full Adders Design • The unique characteristic : Switching voltage can be varied according to the selected capacitor values • The key factor is to start with a unit capacitance value • Gate area that for 1.5mm (edge) standard CMOS process varies from 580aF/mm2 to 620aF/mm2 for different runs • Average value has been used which is 596aF/mm2

  31. Capacitors Design

  32. Resistors Addition and Design All High inputs • Most circuit simulators replace the input coupling capacitors with open circuits during DC analysis • Capacitive input gate gives a degraded output level when inputs are not uniform • Solution • Use a very high resistor element as between the capacitive inputs gate and voltage inputs elements All Low inputs Not Uniform inputs

  33. Width Design • Parasitic capacitances are in the range of 100fF-400fF • These capacitances cause rise and fall times of input signals to increase • It is therefore necessary to resize the transistors by increasing their W/L ratios

  34. MIN FA Using Capacitors

  35. Average Currents & Delay

  36. Threshold Logic (TLG)

  37. Threshold Logic (TLG)

  38. Comparison • The 1 bit CMOS full Adder Structure has a minimum power consumption

  39. Sub-threshold

  40. 1-Bit Full Adder Circuit • Using Pass Transistor in structure level design

  41. Sub-threshold

  42. Sub-threshold behavior of the MOS • As the VTH decreases: • ID leakage • Static power • Circuit instability • ID should fall to zero very quickly after VGS falls below VTH • S measures by how much VGS has to be reduced for the drain current to drop by a factor of 10

  43. Applying Sub-Threshold Technique For 1-Bit FA • Reduce the voltage of the circuit From 2 to 0.3 V • Design width: • By iteration

  44. Sub-Threshold Results

  45. Sub-Threshold Results • There is always a tradeoff between power consumption and the time delay for the full adder.

  46. Project Realization & Performance Optimization • The power in full adder structure is minimized with the passage of time • Started with the standard full adder structure (mirror Full Adder) the power consumption was higher than expected • This led to start concerning about the power issue by looking forward new designs of full adder structures that have low power consumption • As a results of this concern, it is founded today some full adder structures that are designed to consumed low power by making them contain the elements that help to reduce the power

  47. Low Power Structure • 1 bit CMOS Full Adder is a low power structure that contains a pass transistor • The pass transistor helped in reducing the power by eliminating the short circuit currents since there is no voltage source and ground in it composition • Minority gate Full Adder using the capacitors • Using capacitors will reduce the power consumption because they replace the transistors, so the amount of the short circuit currents is reduced

  48. Conclusion • The objective of this project was achieved • The low power full adder design can be achieved by applying the low power techniques to the structure • Pass transistor and capacitive inputs elements • Low voltage sources • Sub threshold to any full adder structure • The 1 bit CMOS full Adder Structure is the one that must be used when searching for low power consumption.

  49. Thanks Any Question

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