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PAN Feasibility: The BodyLAN TM Experience PowerPoint Presentation
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PAN Feasibility: The BodyLAN TM Experience
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  1. PAN Feasibility:The BodyLANTM Experience GTE Internetworking - BBN Technologies 733 Concord AvenueCambridge, MA 02138 Rick LaRowe(rlarowe@bbn.com) I N T E R N E T W O R K I N G POWERED BY BBN Rick LaRowe, GTE

  2. Personal Area Networks Driving requirements include: • Very low power consumption • Very small devices (including peripherals, sensors, etc.) • Easy integration into devices (minimal SW) • Cross-network interference tolerance • Very low cost Simplifying characteristics include: • Data rate requirement is relatively low • Range is short (2-10 meters) Rick LaRowe, GTE

  3. PEA PEA HUB PEA PEA PEA BodyLAN Topology • For simplicity, a STAR topology is employed. • The Hub is at the centerand runs the show. • Around the edge arePersonal ElectronicAccessories (PEAs) Rick LaRowe, GTE

  4. S B H T T E E A O C A PDU A T A K R C C R DATA D E C K E O E S N N R P Key Characteristics • Simple TDMA structure: • Cross-network interference: • CDMA-like burst spacing using Optical Orthogonal Coding • Frequency agility Rick LaRowe, GTE

  5. Other Key Attributes • PAN requirements demand only small networks; 7-bit MAC address is sufficient. • Dynamic device attachment supported via a form ofslotted Aloha layered on top of the TDMA structure. • Ad Hoc networking easily supported: any device can function as a Hub. • Prioritorized bandwidth allocation is easily achieved via Hub token allocation mechanism. (Partly demand-driven via Status Response messages from PEAs.) • Design readily enables single-chip Data-Link and MAC implementation. Rick LaRowe, GTE

  6. PPC 403 BodyLAN BodyLAN PC, HPC, RS-232 Host Digital RF or Processor Control Transceiver Sensor Proof-of-Concept Demo • Demonstrated with two real applications in early 1998. • Basic structure: • PowerPC (PPC) runs the device driver and protocol stack. (PPC selected since needed to run Inertial Navigation code used by a demonstration sensor PEA.) • Digital board contains an Altera PLD with MAC layer implementation and debug logic. • RF transceiver a small discrete implementation. Rick LaRowe, GTE

  7. Host Processor & Digital PLD Rick LaRowe, GTE

  8. Characteristics of POC Demo • Fully operational, with good performance • Dynamic attachment / detachment works • Dynamic bandwidth allocation over TDMA structure • 100mA with PowerPC @ 25MHzTransceiver draws 10mA when running (xmit/recv)PLD draws about 15mA (ASIC est. @ 500mA)(lots of debug and test support, no board-level optimization) • Range adjusted to about 2m, have run up to about 5m Rick LaRowe, GTE

  9. The End Any Questions? Rick LaRowe, GTE